Performance of the wavelet-transform-neural network based receiver for DPIM in diffuse indoor optical wireless links in presence of artificial light interference

Artificial neural network (ANN) has application in communication engineering in diverse areas such as channel equalization, channel modeling, error control code because of its capability of nonlinear processing, adaptability, and parallel processing. On the other hand, wavelet transform (WT) with both the time and the frequency resolution provides the exact representation of signal in both domains. Applying these signal processing tools for channel compensation and noise reduction can provide an enhanced performance compared to the traditional tools. In this paper, the slot error rate (SER) performance of digital pulse interval modulation (DPIM) in diffuse indoor optical wireless (OW) links subjected to the artificial light interference (ALI) is reported with new receiver structure based on the discrete WT (DWT) and ANN. Simulation results show that the DWT-ANN based receiver is very effective in reducing the effect of multipath induced inter-symbol interference (ISI) and ALI

Application of wavelets and artificial neural network for indoor optical wireless communication systems

Abstract This study investigates the use of error control code, discrete wavelet transform (DWT) and artificial neural network (ANN) to improve the link performance of an indoor optical wireless communication in a physical channel. The key constraints that barricade the realization of unlimited bandwidth in optical wavelengths are the eye-safety issue, the ambient light interference and the multipath induced intersymbol interference (ISI). Eye-safety limits the maximum average transmitted optical power. The rational solution is to use power efficient modulation techniques. Further reduction in transmitted power can be achieved using error control coding. A mathematical analysis of retransmission scheme is investigated for variable length modulation techniques and verified using computer simulations. Though the retransmission scheme is simple to implement, the shortfall in terms of reduced throughput will limit higher code gain. Due to practical limitation, the block code cannot be applied to the variable length modulation techniques and hence the convolutional code is the only possible option. The upper bound for slot error probability of the convolutional coded dual header pulse interval modulation (DH-PIM) and digital pulse interval modulation (DPIM) schemes are calculated and verified using simulations. The power penalty due to fluorescent light interference (FL I) is very high in indoor optical channel making the optical link practically infeasible. A denoising method based on a DWT to remove the FLI from the received signal is devised. The received signal is first decomposed into different DWT levels; the FLI is then removed from the signal before reconstructing the signal. A significant reduction in the power penalty is observed using DWT. Comparative study of DWT based denoising scheme with that of the high pass filter (HPF) show that DWT not only can match the best performance obtain using a HPF, but also offers a reduced complexity and design simplicity. The high power penalty due to multipath induced ISI makes a diffuse optical link practically infeasible at higher data rates. An ANN based linear and DF architectures are investigated to compensation the ISI. Unlike the unequalized cases, the equalized schemes don‘t show infinite power penalty and a significant performance improvement is observed for all modulation schemes. The comparative studies substantiate that ANN based equalizers match the performance of the traditional equalizers for all channel conditions with a reduced training data sequence. The study of the combined effect of the FLI and ISI shows that DWT-ANN based receiver perform equally well in the present of both interference. Adaptive decoding of error control code can offer flexibility of selecting the best possible encoder in a given environment. A suboptimal ?soft‘ sliding block convolutional decoder based on the ANN and a 1/2 rate convolutional code with a constraint length is investigated. Results show that the ANN decoder can match the performance of optimal Viterbi decoder for hard decision decoding but with slightly inferior performance compared to soft decision decoding. This provides a foundation for further investigation of the ANN decoder for convolutional code with higher constraint length values. Finally, the proposed DWT-ANN receiver is practically realized in digital signal processing (DSP) board. The output from the DSP board is compared with the computer simulations and found that the difference is marginal. However, the difference in results doesn‘t affect the overall error probability and identical error probability is obtained for DSP output and computer simulations

FPGA-based DOCSIS upstream demodulation

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced

Contributions to adaptive equalization and timing recovery for optical storage systems

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