Development of micromachined millimeter-wave modules for next-generation wireless transceiver front-ends

This thesis discusses the design, fabrication, integration and characterization of millimeter wave passive components using polymer-core-conductor surface micromachining technologies. Several antennas, including a W-band broadband micromachined monopole antenna on a lossy glass substrate, and a Ka-band elevated patch antenna, and a V-band micromachined horn antenna, are presented. All antennas have advantages such as a broad operation band and high efficiency. A low-loss broadband coupler and a high-Q cavity for millimeter-wave applications, using surface micromachining technologies is reported using the same technology. Several low-loss all-pole band-pass filters and transmission-zero filters are developed, respectively. Superior simulation and measurement results show that polymer-core-conductor surface micromachining is a powerful technology for the integration of high-performance cavity, coupler and filters. Integration of high performance millimeter-wave transceiver front-end is also presented for the first time. By elevating a cavity-filter-based duplexer and a horn antenna on top of the substrate and using air as the filler, the dielectric loss can be eliminated. A full-duplex transceiver front-end integrated with amplifiers are designed, fabricated, and comprehensively characterized to demonstrate advantages brought by this surface micromachining technology. It is a low loss and substrate-independent solution for millimeter-wave transceiver integration.Ph.D.Committee Chair: John Papapolymerou; Committee Chair: Manos Tentzeris; Committee Member: Gordon Stuber; Committee Member: John Cressler; Committee Member: John Z. Zhang; Committee Member: Joy Laska

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Wireless Testing of Integrated Circuits.

Integrated circuits (ICs) are usually tested during manufacture by means of automatic testing equipment (ATE) employing probe cards and needles that make repeated physical contact with the ICs under test. Such direct-contact probing is very costly and imposes limitations on the use of ATE. For example, the probe needles must be frequently cleaned or replaced, and some emerging technologies such as three-dimensional ICs cannot be probed at all. As an alternative to conventional probe-card testing, wireless testing has been proposed. It mitigates many of the foregoing problems by replacing probe needles and contact points with wireless communication circuits. However, wireless testing also raises new problems which are poorly understood such as: What is the most suitable wireless communication technique to employ, and how well does it work in practice? This dissertation addresses the design and implementation of circuits to support wireless testing of ICs. Various wireless testing methods are investigated and evaluated with respect to their practicality. The research focuses on near-field capacitive communication because of its efficiency over the very short ranges needed during IC manufacture. A new capacitive channel model including chip separation, cross-talk, and misalignment effects is proposed and validated using electro-magnetic simulation studies to provide the intuitions for efficient antenna and circuit design. We propose a compact clock and data recovery architecture to avoid a dedicated clock channel. An analytical model which predicts the DC-level fluctuation due to the capacitive channel is presented. Based on this model, feed-forward clock selection is designed to enhance performance. A method to select proper channel termination is discussed to maximize the channel efficiency for return-to-zero signaling. Two prototype ICs incorporating wireless testing systems were fabricated and tested with the proposed methods of testing digital circuits. Both successfully demonstrated gigahertz communication speeds with a bit-error rate less than 10^−11. A third prototype IC containing analog voltage measurement circuits was implemented to determine the feasibility of wirelessly testing analog circuits. The fabricated prototype achieved satisfactory voltage measurement with 1 mV resolution. Our work demonstrates the validity of the proposed models and the feasibility of near-field capacitive communication for wireless testing of ICs.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/93993/1/duelee_1.pd

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

RF-MEMS for high-performance and widely reconfigurable passive components – A review with focus on future telecommunications, Internet of Things (IoT) and 5G applications

Abstract Since its first discussions in literature during late '90s, RF-MEMS technology (i.e. Radio Frequency MicroElectroMechanical-Systems) has been showing uncommon potential in the realisation of high-performance and widely reconfigurable RF passives for radio and telecommunication systems. Nevertheless, against the most confident forecasts sparkling around the successful exploitation of RF-MEMS technology in mass-market applications, with the mobile phone segment first in line, already commencing from the earliest years of the 2000s, the first design wins for MEMS-based RF passives have started to be announced just in late 2014. Beyond the disappointment of all the most flattering market forecasts and, on the other hand, the effective employment of RF-MEMS in niche applications (like in very specific space and defence scenarios), there were crucial aspects, not fully considered since the beginning, that impaired the success of such a technology in large-market and consumer applications. Quite unexpectedly, the context has changed rather significantly in recent years. The smartphones market segment started to generate a factual need for highly reconfigurable and high-performance RF passive networks, and this circumstance is increasing the momentum of RF-MEMS technology that was expected to take place more than one decade ago. On a broader landscape, the Internet of Things (IoT) and the even wider paradigm of the Internet of Everything (IoE) seem to be potential fields of exploitation for high-performance and highly reconfigurable passive components in RF-MEMS technology. This work frames the current state of RF-MEMS market exploitation, analysing the main reasons impairing in past years the proper employment of Microsystem technology based RF passive components. Moreover, highlights on further expansion of RF-MEMS solutions in mobile and telecommunication systems will be briefly provided and discussed

IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of IC and antenna. Limited transistor output power at mm-wave requires multi-element arrays to satisfy communication and radar link budgets. This dissertation presents a wafer-scale compatible IC-antenna co-integration for efficient and scalable mm-wave antenna interfaces. The proposed IC-antenna co-integration approach is demonstrated through single antenna transmitters, a concurrent dual-polarization receiver front-end and polarization-duplex transmitter/receiver front-end. Chapter 2 discusses the challenge of mm-wave IC-antenna interfaces with prior art including antenna-in-package (AiP) and on-chip antennas. The 60 GHz efficient, scalable and wafer-scale compatible IC-antenna co-integration approach is presented demonstrating wide bandwidth and large efficiency which are comparable to system-level AiP techniques at a lower cost and fabrication complexity. Chapter 3 extends the proposed approach to a concurrent 60 GHz dual-polarization receiver front-end for short-range imaging/communication applications and polarization diversity based MIMO links. Active cancellation between orthogonal polarizations is adopted to achieve ∼ 30 dB cross-polarization leakage cancellation and concurrent dual-pol reception. Chapter 4 presents a 60 GHz simultaneous transmit and receive front-end to achieve efficient polarization-duplex operation based on dual-polarization IC-antenna co-integration. Transmitter leakage is suppressed at receiver input and output by intrinsic antenna isolation and a feed-forward passive canceller. Total average self-interference cancellation >40 dB is achieved for 1.07 GHz RF bandwidth at 60 GHz in the presence of a reflector