An Offset Cancelation Technique for Latch Type Sense Amplifiers

An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

1.25 Gbit/s ITU-T G.984.2 burst-mode transimpedance amplifier without reset pins

A

An Artefact suppressing fast-recovery myoelectric amplifier

An amplifier for recording myoelectric signals using surface electrodes has been developed. The special features are suppression of stimulation artefacts and motion artefacts from electrodes. It is designed for recording of myoelectric signals from a muscle that is being stimulated with short impulses. The artifact suppression is achieved by using fast-recovery instrumentation amplifiers and having a nonlinear feedback loop for automatic compensation of changes in DC-offse

Operational amplifiers for use in nuclear spectroscopy

Operational amplifiers for nuclear spectroscop

High-extinction-ratio resonant cavity polarizer for quantum-optics measurements

The use of a high-finesse Fabry-Perot ring cavity with an odd number of reflections as a high-extinction-ratio resonant polarizer is shown. Experimental results from quantum-noise measurements using resonant cavities as spatial and spectral filters and precision polarizers are presented

A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

Compensated Current Injection circuit, theory and applications

This paper presents a detailed description, analysis and example of practical application of a wide frequency band voltage-to-current converter. The converter is characterized by a combination of positive and negative feedback loops. This feature allows compensation for parasitic impedance connected in parallel with the useful load, which in turn keeps an excitation current flowing through the useful load independent of its impedance. The simplicity of the circuit and its good electrical properties are additional advantages of the scheme.Comment: 9 pages and 7 figures in one PDF fil

High Gain Amplifier with Enhanced Cascoded Compensation

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated using a 0.5 μm technology, resulting, for a load of 45 pF and supply voltage of 1.65 V, in open-loop-gain of 129 dB, 23 MHz of gain-bandwidth product, 60o phase margin, 675 μW power consumption and 1% settling time of 28 ns

Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology

This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW