AN EFFECTIVE APPROACH OF BILATERAL FILTER IMPLEMENTATION IN SPARTAN-3 FIELD PROGRAMMABLE GATE ARRAY

This paper presents the Field Programmable Gate Array (FPGA) implementation of Bilateral Filter, in order to achieve high performance and low power consumption. Bilateral filtering is a technique to smooth images while preserving edges by means of a nonlinear combination of nearby image values. This method is nonlinear, local, and simple. We give an idea that bilateral filtering can be accelerated by bilateral grid scheme that enables fast edge-aware image processing. Nowadays, most of the applications require real time hardware systems with large computing potentiality for which fast and dedicated Very Large Scale Integration (VLSI) architecture appears to be the best possible solution. While it ensures high resource utilization, that too in cost effective platforms like FPGA, designing such architecture does offers some flexibilities like speeding up the computation by adapting more pipelined structures and parallel processing possibilities of reduced memory consumptions. Here we have developed an effective approach of bilateral filter implementation in Spartan-3 FPGA

An Image Enhancement Approach to Achieve High Speed Using Adaptive Modified Bilateral Filter for Satellite Images Using FPGA

For real time application scenarios of image processing, satellite imaginary has grown more interest by researches due to the informative nature of image. Satellite images are captured using high quality cameras. These images are captured from space using on-board cameras. Wrong ISO setting, camera vibrations or wrong sensory setting causes noise. The degraded image can cause less efficient results during visual perception which is a challenging issue for researchers. Another reason is that noise corrupts the image during acquisition, transmission, interference or dust particles on the scanner screen of image from satellite to the earth stations. If quality degraded images are used for further processing then it may result in wrong information extraction. In order to cater this issue, image filtering or denoising approach is required. Since remote sensing images are captured from space using on-board camera which requires high speed operating device which can provide better reconstruction quality by utilizing lesser power consumption. Recently various approaches have been proposed for image filtering. Key challenges with these approaches are reconstruction quality, operating speed, image quality by preserving information at edges on image. Proposed approach is named as modified bilateral filter. In this approach bilateral filter and kernel schemes are combined. In order to overcome the drawbacks, modified bilateral filtering by using FPGA to perform the parallelism process for denoising is implemented

Low Latency Event-Based Filtering and Feature Extraction for Dynamic Vision Sensors in Real-Time FPGA Applications

Dynamic Vision Sensor (DVS) pixels produce an asynchronous variable-rate address-event output that represents brightness changes at the pixel. Since these sensors produce frame-free output, they are ideal for real-time dynamic vision applications with real-time latency and power system constraints. Event-based ltering algorithms have been proposed to post-process the asynchronous event output to reduce sensor noise, extract low level features, and track objects, among others. These postprocessing algorithms help to increase the performance and accuracy of further processing for tasks such as classi cation using spike-based learning (ie. ConvNets), stereo vision, and visually-servoed robots, etc. This paper presents an FPGA-based library of these postprocessing event-based algorithms with implementation details; speci cally background activity (noise) ltering, pixel masking, object motion detection and object tracking. The latencies of these lters on the Field Programmable Gate Array (FPGA) platform are below 300ns with an average latency reduction of 188% (maximum of 570%) over the software versions running on a desktop PC CPU. This open-source event-based lter IP library for FPGA has been tested on two different platforms and scenarios using different synthesis and implementation tools for Lattice and Xilinx vendors

High throughput spatial convolution filters on FPGAs

Digital signal processing (DSP) on field- programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30–60 FPS, while maintaining functional flexibility

A study of FPGA-based System-on-Chip designs for real-time industrial application

This paper shows the benefits of the Field Programming Gate Array (FPGAs) in industrial control applications. The author starts by addressing the benefits of FPGA and where it is useful. As well as, the author has done some FPGA’s evaluation researches on the FPGA performing explaining the performance of the FPGA and the design tools. To show the benefits of the FPGA, an industrial application example has been used. The application is a real-time face detection and tracking using FPGA. Face tracking will depend on calculating the centroid of each detected region. A DE2-SoC Altera board has been used to implement this application. The application based on few algorithms that filter the captured images to detect them. These algorithms have been translated to a Verilog code to run it on the DE2-SoC boar

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

FPGA implementation of circular spatial filter under high noise variance conditions

The noise in digital images is additive in nature in various cases. Such kind of noise is called to as Additive White Gaussian Noise (AWGN). This noise gets into image while transmission, reception, storage and retrieval It is difficult to suppress AWGN because it corrupts more or less all the pixels in a image. Some filters such mean filter had been proposed to suppress AWGN but in most cases it incorparates a blurring effect in the image. Image denoising is usually done before display or further processing like feature extraction, segmentation, object identification, texture analysis, etc. The intention of denoising is to suppress the noise efficiently and retaining the edges and other necessary features as far as possible.Many efficient digital image filters are found that perform well under low noise conditions. But in the cases of moderate and high noise conditions their performance is limited. Thus, it is felt that there is sufficient scope to investigate and develop quite efficient. And proposed a spatial filter named as circular spatial filter which performs well under high noise conditions. Suppose CSF has to be used for real time applications such as before displaying the video on HDTV a real time application. It is hard to implement this algorithm on a general purpose computer where high amount of concurrency is needed. So we have chosen FPGA as a target which is suitable for video and image processing. Here we chose virtex-5 Xilinx board to implement the algorithm. The performance of the designed filters is compared with the existing filters and the MATLAB simulation [1] in terms of peak-signal-to noise ratio, root-mean-squared error

A FPGA/DSP based ultrasound system for tumor detection

This work presents a method of detection of size and location of tumor using ultrasound transmission. The system utilizes Quantitative Ultrasound (QUS) which means sending an ultrasound signal from a transmitter and receiving it at multiple receivers. This received signal is analyzed for echogenic as well as echolucent tumors to differentiate between the two along with non-tumorous sample and also for delay, signal distortion to determine the size/location of the tumor. This analysis is further implemented using Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) technologies. The proposed detection system utilizes Low Transient Pulse (LTP) technique. In this co-design architecture, the DSP carries out analysis of received demodulated signal at a lower speed while the FPGA runs at 62.5MHz for the generation of LTP signal and to demodulate bandpass ultrasonic signal sampled at 1MHz which interrupts DSP at every 1µS. This work elaborates the implementation of Quadrature Amplitude Modulation (QAM) receiver on FPGA for received signal from ultrasound detector. LTP is applied to the tumor samples through the transmitter and the received signal at ultrasonic receiver is passed through QAM to get different maxima (peaks) which are then further used for calculation of the location and subsequently, the size of the tumor using DSP. This dual platform co-design demonstrates application of a FPGA/DSP platform for the generation of low transient pulse as well as processing of the received signal