A 64-Channel Mixed-Signal Data Acquisition System for a Solid-State High Efficiency Neutron Detector Array

This thesis presents the design of multiple analog and digital blocks required to implement a desired solid-state data acquisition system for the High Efficiency Neutron Detector Array (HENDA) project under the Spallation Neutron Source (SNS) at Oak Ridge National Laboratory (ORNL). This system encloses and is an extension of prior work described in [1] and [2]. The first prototype chip, named Patara, contained a charge sensitive front-end amplifier [2], and a semi-Gaussian shaper with baseline restore circuitry [1]. Patara III, described in this thesis, involved the addition of the following system components; two comparators, a selectable synchronous/asynchronous digital backend, priority and binary encoders, nine LVDS drivers/receivers, three 8-bit current driven calibration DAC’s, two BGR’s, and a 99-bit serial shift register with channel test-mode circuitry. The design approach for all major blocks will be discussed along with overall system simulations. In addition, the testing procedure and associated measured results will be summarized illustrating a successful system design. This ASIC was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-μm process available through MOSIS

Exploring Liquid Computing in a Hardware Adaptation : Construction and Operation of a Neural Network Experiment

Future increases in computing power strongly rely on miniaturization, large scale integration, and parallelization. Yet, approaching the nanometer realm poses new challenges in terms of device reliability, power dissipation, and connectivity - issues that have been of lesser concern in today's prevailing microprocessor implementations. It is therefore necessary to pursue the research on alternative computing architectures and strategies that can make use of large numbers of unreliable devices and only have a moderate power consumption. This thesis describes the construction of an experiment dedicated to exploring silicon adaptations of artificial neural network paradigms for their general applicability, power efficiency, and fault-tolerance. The presented setup comprises peripheral electronics, programmable logic, and software to accommodate a mixed-signal CMOS microchip implementing a flexible perceptron with 256 McCulloch-Pitts neurons. This neural network experiment is used to explore a recent strategy that allows to access the power of recurrent network topologies. While it has been conjectured that this liquid computing is suited for hardware implementations, this first time adaptation to a CMOS neural network affirms this claim. Not only feasibility but also tolerance to substrate variations and robustness to faults during operation are demonstrated

Three dimentional control of a diode based laser cutter

Includes bibliographical referencesLaser cutting is a widely used technology in many areas of industry and research. Conventional laser cutters only offer control of two axes and either cut through a material or rudimentary control of the third dimension is possible by varying the power, pulse rate and travel rate of the laser beam. These rudimentary three-dimensional systems (often called 2.5D laser cutters) do not incorporate any feedback mechanism to control the depth of cut. The idea of measuring distance using diode lasers (and other laser technologies) is a relatively mature technology and is common to various consumer and industrial products. Recently diode lasers have become powerful enough to perform as laser cutters allowing a merger of these technologies. The aim of this project is to verify the concept of using a laser diode to achieve both material processing and distance measurement. This would allow the creation of a full three-dimension laser cutting machine that is capable of accurate material processing in all three dimensions. This would also offer the ability to cut non-homogenous materials, such as timber, which current ‘2.5D’ laser cutters are unable to cut with any accuracy. A gantry system was designed and constructed, which was able to move the laser cutting toolhead in the x-y plane, using stepper motors and a belt-driven drive system. A 2W single emitter laser diode was used for both laser cutting and distance measurement. Optics were designed and assembled that focused the laser onto the workpiece and directed light reflected back from the workpiece onto a photodiode. Laser driver circuitry was constructed to control the DC current of the laser and to modulate the laser power at the high frequencies required for accurate phase shift measurements. A photodetector and phase shift measurement circuit was designed, simulated and constructed. The phase shift circuit amplified the signal from the light reflected off the workpiece and then compared that signal to a reference signal in order to determine the phase shift between the two. An Atmel® ATmega2560 microcontroller was used to control the gantry, laser driver circuitry and to measure the phase shift output of the phase detector circuitry. Software written in MATLAB® was used to command the microcontroller and to interpret the data received from the microcontroller The photo sensor circuit was not sensitive enough to detect the weak signals that were present when the workpiece had a low reflectivity but was able to be tested using reflective tape. On the other hand the laser diode was not powerful enough to cut reflective tape as it absorbs very little energy from the laser. Nevertheless, the same laser diode was used, without changing any configuration other than the workpiece material, to measure distance and to cut materials. Testing of both the materials processing ability and the distance measurement ability were carried out. Many aspects of each of these major functions were tested, individually and together, in order to determine the areas that performed well and those that need more research. In conclusion, this project was able to verify the concept of a three-dimensionally controlled diode powered laser cutter. Future work will be needed before a practical and useful laser cutter can be built but this project should prove a good starting point for any such future work

Design of a low-cost high speed data capture card for the Hubble Sphere Hydrogen Survey

Includes bibliographical references (leaves 101-105).This thesis describes the design and implementation of a low-cost high speed data capture card for the Hubble Sphere Hydrogen Survey (HSHS). The Hubble Space Hydrogen Survey was initiated in an effort to build a low-cost cylindrical radio telescope for an all sky redshift survey with the observational goal to produce a 3-dimensional mapping of the bulk Hubble Sphere using Hydrogen 21cm emissions. This dissertation ï¬ rst investigates the system design to see how each of the user speciï¬ cations set by the planning team could be achieved in terms of design decisions, component selection and schematic capture. The final design. AstroGIG, satisï¬ es the user speciï¬ cations by capturing data up to a full power bandwidth of 1.7GHz with an instantaneous bandwidth of ≤ 250MHz white maximizing the dynamic range. AstroGIG buffers, processes, stores and ï¬ nally transmits the data through a 4-lane PCI-Express interface to a standard PC where the majority of the processing is performed. The system implementation is then described where issues relating to the process of transforming schematics into a physical PCB, and HSHS integration are discussed. The design is veriï¬ ed through Hyperlynx simulations to give a high degree of certainty that physical implementation and production would be successful. Results from tests on the actual hardware characterizing the overall system performance are presented. Conclusions are drawn based on these results and suggestions for future work and design improvements are recommended

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

Development, Optimisation and Characterisation of a Radiation Hard Mixed-Signal Readout Chip for LHCb

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007

A Current-Mode Multi-Channel Integrating Analog-to-Digital Converter

Multi-channel analog to digital converters (ADCs) are required where signals from multiple sensors can be digitized. A lower power per channel for such systems is important in order that when the number of channels is increased the power does not increase drastically. Many applications require signals from current output sensors, such as photosensors and photodiodes to be digitized. Applications for these sensors include spectroscopy and imaging. The ability to digitize current signals without converting currents to voltages saves power, area, and the design time required to implement I-to-V converters. This work describes a novel and unique current-mode multi-channel integrating ADC which processes current signals from sensors and converts it to digital format. The ADC facilitates the processing of current analog signals without the use of transconductors. An attempt has been made also to incorporate voltage-mode techniques into the current-mode design so that the advantages of both techniques can be utilized to augment the performance of the system. Additionally since input signals are in the form of currents, the dynamic range of the ADC is less dependant on the supply voltage. A prototype 4-channel ADC design was fabricated in a 0.5-micron bulk CMOS process. The measurement results for a 10Ksps sampling rate include a DNL, which is less than 0.5 LSB, and a power consumption of less than 2mW per channel

On-detector electronics for high speed data transport, control and power distribution for the LHCb VELO and ATLAS Pixel Upgrades

The Large Hadron Collider (LHC) will see an upgrade to higher luminosity to widen the scope of study of particle physics and this will be a major upgrade of the LHC. The LHC collides protons at an energy of 13 TeV in order to study the fundamental components of matter and the forces that bind them together. The High-Luminosity Large Hadron Collider (HL-LHC) will enter service after 2025, increasing the volume of the data for analysis by a factor of 10. The phenomena that physicists are looking for have a very low probability of occurring and this is why a very large amount of data is needed to detect them. Vertexing and tracking sub-detectors for these High Energy Physics (HEP) experiments deliver very high data rates that require multi-gigabit transmission links. Commercial solutions such as optical transmission or wire cabling are investigated, however, due to high radiation environments and low radiation length requirements, electrical transmission with low mass custom designs have to be considered. Designing transmission lines with this requirement does pose a challenge and optical data transmission is used when space and radiation limits allow. The increase in luminosity will produce more data making it possible to study the phenomena in more detail by increasing the number of collisions by a factor of between five and seven. The increase in data will require an enhanced readout system and related electronics to be able to transmit and read out the data for further processing. At the same time powering systems need to be looked at to understand cost effcient and reliable techniques to be able to power such electronics. The thesis focuses on the readout electronics of the LHCb Vertex Locator (known as the 'VELO') Upgrade and the ATLAS Inner Tracker (known as the 'ITk') Upgrade including design of some components of the sub-systems, testing for high-speed data signaling, powering schemes and analysis of PCB designs and scope for improvements. An introduction to the LHC and the four experiments that use its beam - ATLAS, CMS, ALICE and LHCb is outlined. The thesis work is focused on two of these detectors namely ATLAS (A Toroidal LHC ApparatuS) and LHCb (Large Hadron Collider beauty) and these are further explained and details of the sub-systems that make up these detectors are elaborated. Major differences to the upgrade of the experiments is explained highlighting the changes and the main challenges that would need to be addressed. The work on the On-detector electronics of the LHCb VELO Upgrade with details of the design requirements and implementations for the different components is described and test results are presented. Data tapes for carrying high speed data signals and control signals from the front-end chip to the Vacuum Feedthoough (VF) were designed and successfully tested to have a loss of < 10 dB at the Nyquist frequency of 2.5 GHz and a characteristic impedance of approximately 94 Ω which is within the 10% tolerance of 100 Ω for differential signals. Sensitivity to radiation damage as well as additional mass in the detector acceptance were some factors that motivated the design of the Opto Power board (OPB). In addition, there was a need to power the front-end ASICs but from outside the vacuum tank. The OPB was designed to meet these requirements in addition to be more easily accessible for repair and maintenance. The OPB is realised in an 8-layer stackup, with custom designed radiation hard ICs, and was designed for optical to electrical conversion of 20 high-speed data links at 5.12 Gb/s per link to be read by the Off-detector electronics. The board comprises 13 DC-DC converters for powering 12 ASICs, two front-end hybrids and the OPB itself with a total current supply of 26 A. The ATLAS experiment will implement the Inner Tracker (ITk) which is a new tracker to be installed during the major ATLAS Upgrade during Long Shutdown 3. The work on the ATLAS ITK addresses two topics; a novel pixel powering scheme adopting layout techniques for high-speed design. A serial powering scheme was evaluated to be an optimal option and this scheme was tested to understand its scope and implementation in the pixel endcap design and results are presented. A study to understand the existing Crescent Tape PCB layout and techniques to improve the design for high-speed data transmission was evaluated. Methods for analysing high-speed data using S-parameters and eye diagrams, sources of signal degradation and mitigation techniques, are detailed. The laboratory test setup for high-speed measurements with the equipments used is also explained