1,071 research outputs found
Adaptive Efficiency Optimization For Digitally Controlled Dc-dc Converters
The design optimization of DC-DC converters requires the optimum selection of several parameters to achieve improved efficiency and performance. Some of these parameters are load dependent, line dependent, components dependent, and/or temperature dependent. Designing such parameters for a specific load, input and output, components, and temperature may improve single design point efficiency but will not result in maximum efficiency at different conditions, and will not guarantee improvement at that design point because of the components, temperature, and operating point variations. The ability of digital controllers to perform sophisticated algorithms makes it easy to apply adaptive control, where system parameters can be adaptively adjusted in response to system behavior in order to achieve better performance and stability. The use of adaptive control for power electronics is first applied with the Adaptive Frequency Optimization (AFO) method, which presents an auto-tuning adaptive digital controller with maximum efficiency point tracking to optimize DC-DC converter switching frequency. The AFO controller adjusts the DC-DC converter switching frequency while tracking the converter minimum input power point, under variable operating conditions, to find the optimum switching frequency that will result in minimum total loss and thus the maximum efficiency. Implementing variable switching frequencies in digital controllers introduces two main issues, namely, limit cycle oscillation and system instability. Dynamic Limit Cycle Algorithms (DLCA) is a dynamic technique tailored to improve system stability and to reduce limit cycle oscillation under variable switching frequency operation. The convergence speed and stability of AFO algorithm is further improved by presenting the analysis and design of a digital controller with adaptive auto-tuning algorithm that has a variable step size to track and detect the optimum switching frequency for a DC-DC converter. The Variable-Step-Size (VSS) algorithm is theoretically analyzed and developed based on buck DC-DC converter loss model and directed towered improving the convergence speed and accuracy of AFO adaptive loop by adjusting the converter switching frequency with variable step size. Finally, the efficiency of DC-DC converters is a function of several variables. Optimizing single variable alone may not result in maximum or global efficiency point. The issue of adjusting more than one variable at the same time is addressed by the Multivariable Adaptive digital Controller (MVAC). The MVAC is an adaptive method that continuously adjusts the DC-DC converter switching frequency and dead-time at the same time, while tracking the converter minimum input power, to find the maximum global efficiency point under variable conditions. In this research work, all adaptive methods were discussed, theoretically analyzed and its digital control algorithm along with experimental implementations were presented
Analysis And Design Optimization Of Multiphase Converter
Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed
The Experimental Analysis of Predictive Control Scheme in High Frequency Gate Driver Design
Predictive Dead Time Control Scheme is used in gate driver to overcome the problems relating to the td. This control scheme applies the prediction concept based on the feedback output from the circuit to predict and reduce the tdon the switching cycle of the gate driver. Therefore by using the application of the predictive dead time control scheme, the problem related with the td can be minimized
Ultra-Efficient Cascaded Buck-Boost Converter
This thesis presents various techniques to achieve ultra-high-efficiency for Cascaded-Buck-Boost converter. A rigorous loss model with component non linearity is developed and validated experimentally. An adaptive-switching-frequency control is discussed to optimize weighted efficiency. Some soft-switching techniques are discussed. A low-profile planar-nanocrystalline inductor is developed and various design aspects of core and copper design are discussed. Finite-element-method is used to examine and visualize the inductor design. By implementing the above, a peak efficiency of over 99.2 % is achieved with a power density of 6 kW/L and a maximum profile height of 7 mm is reported. This converter finds many applications because of its versatility: allowing bidirectional power flow and the ability to step-up or step-down voltages in either direction
Highly Integrated Dc-dc Converters
A monolithically integrated smart rectifier has been presented first in this work. The smart rectifier, which integrates a power MOSFET, gate driver and control circuitry, operates in a self-synchronized fashion based on its drain-source voltage, and does not need external control input. The analysis, simulation, and design considerations are described in detail. A 5V, 5-µm CMOS process was used to fabricate the prototype. Experimental results show that the proposed rectifier functions as expected in the design. Since no dead-time control needs to be used to switch the sync-FET and ctrl-FET, it is expected that the body diode losses can be reduced substantially, compared to the conventional synchronous rectifier. The proposed self-synchronized rectifier (SSR) can be operated at high frequencies and maintains high efficiency over a wide load range. As an example of the smart rectifier\u27s application in isolated DC-DC converter, a synchronous flyback converter with SSR is analyzed, designed and tested. Experimental results show that the operating frequency could be as high as 4MHz and the efficiency could be improved by more than 10% compared to that when a hyper fast diode rectifier is used. Based on a new current-source gate driver scheme, an integrated gate driver for buck converter is also developed in this work by using a 0.35µm CMOS process with optional high voltage (50V) power MOSFET. The integrated gate driver consists both the current-source driver for high-side power MOSFET and low-power driver for low-side power iv MOSFET. Compared with the conventional gate driver circuit, the current-source gate driver can recovery some gate charging energy and reduce switching loss. So the current-source driver (CSD) can be used to improve the efficiency performance in high frequency power converters. This work also presents a new implementation of a power supply in package (PSiP) 5MHz buck converter, which is different from all the prior-of-art PSiP solutions by using a high-Q bondwire inductor. The high-Q bondwire inductor can be manufactured by applying ferrite epoxy to the common bondwire during standard IC packaging process, so the new implementation of PSiP is expected to be a cost-effective way of power supply integration
EXPERIMENTAL ANALYSIS OF GATE DRIVE CONTROL SYSTEM FOR SYNCHRONOUS DC/DC CONVERTER
The design of the PCB board is important as it affects the overall
performance of the overall system. The most common problem that affects the
performance and efficiency of the PCB board are partitioning of the circuits, the
problem of interconnecting traces, grounding schemes and thermal management.
Overall, the primary objectives of the project are to understand the process flow of
PCB and to acquire knowledge about PCB fabrication. Meanwhile, the secondary
objectives of the project are to apply high frequency DC-DC Converter on PCB
fabrication and lastly to test and verify the output of PCB fabrication. SRBC-PWM
and SRBC-compensator-AGD are successfully implemented on PCB board. The
knowledge about PCB design is acquired and the problems overcome while
fabricating PCB are managed to overcome
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High efficiency smart voltage regulating module for green mobile computing
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption
COMPARATIVE STUDY OF MULTIPLE CONTROLLER DESIGNS FOR HIGH FREQUENCY CONVERTER
This paper compares the performance of the high frequency converter with controller circuit and without controller circuit. The comparison is done in term of the output ripple voltage and current, output voltage and current and the body diode conduction loss. The reason to do this research is because at high frequency, the Pulse Width Modulator becomes less efficient and produces higher losses, therefore there is a need to find a new controller. The design is tested using a synchronous rectifier buck converter (SRBC) circuit with a switching frequency of 1 MHz. The design and simulation are done with the aid of PSpice software. At the end of the research, it is found that the Compensator with AGD produces the best result
COMPARATIVE ASSESSMENTS OF CONTINUOUS AND SELF-DRIVEN PWM FOR HIGH FREQUENCY CONVERTER DESIGN
In this project the comparison of the continuous gate drivers and self
driven gate drivers' characteristics, performance, operation modes, advantages,
and disadvantages are analyzed and observed. Both of the gate drivers will be
applied at synchronous buck converter, SBC as the output circuit and also with
switching frequency of 1 MHz. PSPICE software is used in designing and
simulating the respective circuit. The comparison is carried out based on the
output voltage, current, node voltage, output ripple voltage and current, gate-tosource
voltage, and body diode conduction loss of the continuous and self-driven
gate drivers. Type III compensator and AGD are applied to both switches in the
SBC circuit. At the end of the simulation, adding AGD to the SBC reduces the
dead time, body diode conduction and also cross-conduction losses in DCM. SBC
shows an improvement up to 9.70% and 9.78 %on output voltage, current and
also has virtually zero on the body diode conduction losses when both
compensator and AGD are applied. For CCM and DCM, it is observed that SBC
with COD, AGD and compensator-AGO produce high output current in CCM
compared to DCM. COD with SBC, the output current in CCM improves 12.22 %
compared to DCM. Besides, AGD with SBC is the least preferable circuit
compared to compensator-AGO, MPPT-Vpulse, parallelism, and COD because of
the lower output voltage and current produced, higher output ripple for voltage
and current, and higher body diode conduction loss in the SBC. Here the output
voltage and current is reduced to 15.30 % and 15.21 % respectively as it is
compared to MPPT-Vpulse
THE STUDY AND ANALYSIS OF MPPT CONTROLLER FOR SRBC
This work is about designing Maximum Power Point Tracker (MPPT) with
Synchronous Rectifier Buck Converter (SRBC) circuit where the main purpose is to improve
the performance and increase the output voltage and current. The MPPT controller
controls the output current of the input (usually solar array) so that the output power
converges on the maximum based on the linearity between the maximum output
power and the optimal current. In this work, MPPT' s characteristics, performance,
operation modes, advantages, and disadvantages are analyzed and observed. Then,
combination ofMPPT and adaptive gate drive (AGD) will be applied to SRBC as the
output circuit. PSPICE software is used in designing and simulating both circuits. The
comparison is carried out based on the average output voltage and current, node
voltage, output ripple voltage and current, gate-to-source voltage, and body diode
conduction loss of the MPPT circuit and MPPT with AGD circuit. The details are
discussed thoroughly that include limitations and advantages in the design of the controllers
using I MHz switching frequency. It is found that by implementing MPPT controller
with SRBC, the output voltage and output current have increased by approximately
12%- 13% for both CCM and DCM conditions. Besides that, it also reduces output
voltage ripple and current around 70 % for CCM mode. However, in DCM condition,
the output peak-to-peak ripple for both voltage and current have increased by 20 %
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