Active Filter for Single-Phase Power System

This study investigates the application and functionality of pure active power filters for current compensation in single-phase power systems. A small scale proof of concept design was constructed, using components which were studied, justified, and chosen based upon desired characteristics. The components were simulated on several different platforms to analyze their potential design feasibility. Based upon the study and simulation of this system the pure active power filter can be confirmed as a reputable form of harmonic filtering for single-phase power systems

Test Strategies for Embedded ADC Cores in a System-on-Chip, A Case Study

Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to the external tester. IEEE Standard 1500 provides efficient test infrastructure for testing digital cores; however, its applications in mixed-signal core test remain an open issue. In this paper we address the problem of implementing BIST of a mixed-signal core in a IEEE Std 1500 test wrapper and discuss advantages and drawbacks of different test strategies. While the case study is focused on histogram based test of ADC, test strategies of other types of mixed-signal cores related to trade-off between performance (i.e., test time) and required resources are likely to follow similar conclusions

Indoor Positioning Using Acoustic Pseudo-Noise Based Time Difference of Arrival

The Global Positioning System (GPS) provides good precision on a global scale, but is not suitable for indoor applications. Indoor positioning systems (IPS) aim to provide high precision position information in an indoor environment. IPS has huge market opportunity with a growing number of commercial and consumer applications especially as Internet of Things (IoT) develops. This paper studies an IPS approach using audible sound and pseudo-noise (PN) based time difference of arrival (TDoA). The system’s infrastructure consists of synchronized speakers. The object to be located, or receiver, extracts TDoA information and uses multilateration to calculate its position. The proposed IPS utilizes sound waves since they travel much slower compared to electromagnetic waves, allowing for easier measurements. Additionally, the audible spectrum has a large availability of low directivity speakers and microphones allowing for a large coverage area compared to highly directive ultrasonic transceivers. This paper experimentally evaluates the feasibility of the proposed IPS

A Low-Power, Low-Area 10-Bit SAR ADC with Length-Based Capacitive DAC

A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 µm^2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained. Adviser: Sina Balkir and Michael Hoffma