38 research outputs found
Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology
Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation
Estudio del diseño de un circuito de voltaje de referencia para aplicaciones de bajo voltaje y bajo consumo de energía
Este trabajo de investigación describe el funcionamiento de los circuitos que permiten la
generación de un voltaje de referencia estable ante variaciones en la temperatura y el voltaje de
alimentación. Las topologías clásicas de circuitos de voltaje de referencia limitan el voltaje que
entregan a valores cercanos a 1.2 V, impidiendo que aplicaciones de menor voltaje puedan hacer
uso de dichos circuitos.
El principal inconveniente yace en que las topologías clásicas de estos circuitos limitan el voltaje
que entregan a valores cercanos a 1.2 V. Actualmente muchos circuitos integrados se diseñan para
operar con voltajes menores a 1.2 V, de modo que es necesario plantear las consideraciones que
permitan el diseño de un circuito de voltaje de referencia de bajo voltaje.
El propósito de este trabajo de investigación es exponer los fundamentos para el diseño de un
circuito de voltaje de referencia. Se desarrolla la teoría que permite la obtención de un voltaje
independiente de la temperatura. Posteriormente se analizan dos topologías: una convencional y
otra de bajo voltaje. Esta última sirve de referencia para el diseño de voltaje de referencia de bajo
voltaje.
En la parte final de esta investigación se enuncian conclusiones sobre el marco teórico revisado.
También se mencionan recomendaciones para el diseño de un circuito de bajo voltaje.Trabajo de investigació
A 0.82V supply and 23.4 ppm/0C current mirror assisted bandgap reference
Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC
CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works
from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW
of power and occupies 73*32µm2 silicon area
Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems
A wireless biomedical telemetry system is a device that collects biomedical signal measurements and transmits data through wireless RF communication. Testing medical treatments often involves experimentation on small laboratory animals, such as genetically modified mice and rats. Using batteries as a power source results in many practical issues, such as increased size of the implant and limited operating lifetime. Wireless power harvesting for implantable biomedical devices removes the need for batteries integrated into the implant. This will reduce device size and remove the need for surgical replacement due to battery depletion. Resonant inductive coupling achieves wireless power transfer in a manner modelled by a step down transformer. With this methodology, power harvesting for an implantable device is realized with the use of a large primary coil external to the subject, and a smaller secondary coil integrated into the implant. The signal received from the secondary coil must be regulated to provide a stable direct current (DC) power supply, which will be used to power the electronics in the implantable device. The focus of this work is on development of an electronic front-end for wireless powering of an implantable biomedical device. The energy harvesting front-end circuit is comprised of a rectifier, LDO regulator, and a temperature insensitive voltage reference. Physical design of the front-end circuit is developed in 0.13um CMOS technology with careful attention to analog layout issues. Post-layout simulation results are presented for each sub-block as well as the full front-end structure. The LDO regulator operates with supply voltages in the range of 1V to 1.5V with quiescent current of 10.5uA The complete power receiver front-end has a power conversion efficiency of up to 29%
Ultra-low power mixed-signal frontend for wearable EEGs
Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients.
All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study.
The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%.
The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces
LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES
The research work described in this thesis was focused on finding novel techniques to
implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit
technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG
signal and several bio-medical signals are sensed from the human body through a pair
of electrodes. The electrical characteristics of the very small amplitude (1u-10mV)
signals are corrupted by random noise and have a significant dc offset. 50/60Hz power
supply coupling noise is one of the biggest cross-talk signals compared to the thermally
generated random noise. These signals are even AFE composed of an Instrumentation
Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main
function of the AFE is to convert the weak electrical Signal into large signals whose
amplitude is large enough for an Analog Digital Converter (ADC) to detect without having
any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal
amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver
needs an accurate and temperature-independent reference voltage and current for the
ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to
consume as low power as possible to enable these circuits to be powered from the
battery.
The work started with analysing the existing circuit techniques for the circuits
mentioned above and finding the key important improvements required to reach the
target specifications. Previously proposed IA is generated based on voltage mode signal
processing. To improve the CMRR (119dB), we proposed a current mode-based IA with
an embedded DC cancellation technique. State-of-the-art VGA circuits were built based
on the degeneration principle of the differential pair, which will enable the variable gain
purpose, but none of these techniques discussed linearity improvement, which is very
important in modern CMOS technologies. This work enhances the total Harmonic
distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around
the differential pair. Also, this work proposes a low power curvature compensated
bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a
1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and
simulated with all the performance metrics with Cadence (spectre) simulator. The circuit
layout was carried out to study post-layout parasitic effect sensitivity
An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC
Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that
1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes,
2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs,
3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers,
4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications,
5. utilizes a standard CMOS process, to lower manufacturing costs, and
6. is integrated, to consume less board space
has been proposed.
The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC.
The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma
Integrated Circuits for Programming Flash Memories in Portable Applications
Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration
A low power high power supply rejection ratio bandgap reference for portable applications
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 86-87).A multistage bandgap circuit with very high power supply rejection ratio was designed and simulated. The key features of this bandgap include multiple power modes, low power consumption and a novel resistor trimming strategy. This design was completed in deep submicron CMOS technology, and is especially suited for portable applications. The bandgap designed achieves over 90 dB of power supply rejection and less than 17 microvolts of noise without any external filtering. With an external filtering capacitor, this performance is significantly enhanced. In addition, the design includes an efficient voltage-to-current converter and a fast-charge circuit for charging the external capacitor.by Siddharth Sundar.M.Eng