141,596 research outputs found
A Hierachical Infrastrucutre for SOC Test Management
HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system
Design of multimedia processor based on metric computation
Media-processing applications, such as signal processing, 2D and 3D graphics
rendering, and image compression, are the dominant workloads in many embedded
systems today. The real-time constraints of those media applications have
taxing demands on today's processor performances with low cost, low power and
reduced design delay. To satisfy those challenges, a fast and efficient
strategy consists in upgrading a low cost general purpose processor core. This
approach is based on the personalization of a general RISC processor core
according the target multimedia application requirements. Thus, if the extra
cost is justified, the general purpose processor GPP core can be enforced with
instruction level coprocessors, coarse grain dedicated hardware, ad hoc
memories or new GPP cores. In this way the final design solution is tailored to
the application requirements. The proposed approach is based on three main
steps: the first one is the analysis of the targeted application using
efficient metrics. The second step is the selection of the appropriate
architecture template according to the first step results and recommendations.
The third step is the architecture generation. This approach is experimented
using various image and video algorithms showing its feasibility
A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures
This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip
Access and metro network convergence for flexible end-to-end network design
This paper reports on the architectural, protocol, physical layer, and integrated testbed demonstrations carried out by the DISCUS FP7 consortium in the area of access - metro network convergence. Our architecture modeling results show the vast potential for cost and power savings that node consolidation can bring. The architecture, however, also recognizes the limits of long-reach transmission for low-latency 5G services and proposes ways to address such shortcomings in future projects. The testbed results, which have been conducted end-to-end, across access - metro and core, and have targeted all the layers of the network from the application down to the physical layer, show the practical feasibility of the concepts proposed in the project
A Design Methodology for Space-Time Adapter
This paper presents a solution to efficiently explore the design space of
communication adapters. In most digital signal processing (DSP) applications,
the overall architecture of the system is significantly affected by
communication architecture, so the designers need specifically optimized
adapters. By explicitly modeling these communications within an effective
graph-theoretic model and analysis framework, we automatically generate an
optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs
a C description of Input/Output data scheduling, and user requirements
(throughput, latency, parallelism...), and formalizes communication constraints
through a Resource Constraints Graph (RCG). The RCG properties enable an
efficient architecture space exploration in order to synthesize a STAR
component. The proposed approach has been tested to design an industrial data
mixing block example: an Ultra-Wideband interleaver.Comment: ISBN : 978-1-59593-606-
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