Model-based exploration of interactions in the visual cortex

The mammalian visual system is a dynamic and efficient data processing framework. Specifically, the cerebral cortex which is a structured network of cells benefits from an efficient information transmission coding. This thesis presents a model-based exploration of visual cortex in order to expand our current knowledge about brain mechanisms; specifically, the mechanism of information coding behind visual interactions. In the first study, we designed a functional magnetic resonance imaging (fMRI) experiment to explore a possible link between contextual modulation and efficient macroscopic spatial response coding in the visual cortex. The results imply that visual interactions were best explained with a decorrelation model which predicts average modulation strength by fully decorating the spatial fMRI signals.  In the second study, we reviewed a potential approach to relate fMRI activation patterns to neural population activity. We went over existing knowledge about neurovascular coupling as a key point in predicting fMRI signal based on a neural network simulation and provided a sketch which covered practical steps to bridge the gap between mathematical modeling of single neuron responses to neuroimaging data with a mesoscopic biomimetic neural network. The proposed biomimetic neural network provides insight into data processing in cortical neural networks. In the third study, we designed an fMRI experiment and based on the blueprint of the second study simulated a simplified neural network representing the visual cortex. Then, we tried to replicate the experimental fMRI signal by means of this biophysically plausible neural network simulator. Our results highlight the role of dendritic structure of neurons to be able to repeat the experimental fMRI signals with high fidelity. In the fourth study, we used similar simulator as in the third study and tried to replicate expected neural activation pattern based on a well know contextual modulation (area summation function) in primary visual cortex. We anticipated that by getting closer to an activation pattern driven by area summation function, the efficiency of the neural network would be increased. Our results show that spiking frequency, entropy per spike and sparseness (as measures of network efficiency) are all associated with the natural area summation function.  In summary, results of this thesis suggest that contextual modulation is related to efficiency of the visual system. In addition, it is possible to predict fMRI and expected area summation activation pattern by a mesoscopic neural network, however compartmental neurons have a key role to achieve this prediction

Implementation of Image Classifiers in FPGAs

Práce je zaměřena na obrazové klasifikátory a jejich implementaci v FPGA. Klasifikátory dělí na dvě skupiny - slabé a silné klasifikátory. Ve skupině silných klasifikátorů se zaměřuje především na AdaBoost. Ve skupině slabých klasifikátorů jsou probrány základní příznakové klasifikátory, jakými jsou například klasifikátory založené na Haarových nebo Gaborových vlnkách, ale především je kladen důraz na klasifikátory LBP, LRP a LR. Naposled uvedené klasifikátory jsou vhodné pro implementaci v FGPA. Na základě těchto klasifikátorů je navržena pseudo-paralelní architektura. Architektura uvažuje provedení klasifikace v FPGA a následné zpracovávání výsledků v počítači. Navržený klasifikátor je velmi rychlý a každý hodinový cyklus produkuje výstup klasifikace.The thesis deals with image classifiers and their implementation using FPGA technology. There are discussed weak and strong classifiers in the work. As an example of strong classifiers, the AdaBoost algorithm is described. In the case of weak classifiers, basic types of feature classifiers are shown, including Haar and Gabor wavelets. The rest of work is primarily focused on LBP, LRP and LR classifiers, which are well suitable for efficient implementation in FPGAs. With these classifiers is designed pseudo-parallel architecture. Process of classifications is divided on software and hardware parts. The thesis deals with hardware part of classifications. The designed classifier is very fast and produces results of classification every clock cycle.

Object Recognition

Vision-based object recognition tasks are very familiar in our everyday activities, such as driving our car in the correct lane. We do these tasks effortlessly in real-time. In the last decades, with the advancement of computer technology, researchers and application developers are trying to mimic the human's capability of visually recognising. Such capability will allow machine to free human from boring or dangerous jobs

Pengkodean Video 3D Pada FPGA Berbasiskan Xilinx Zynq-7000

Kebutuhan konsumen terhadap teknologi multimedia yang baru dan lebih handal, menggiring pihak industri untuk meningkatkan pelayanan di bidang pemasaran entertainment, sehingga pada muaranya mendorong popularisasi konten video 3D, perangkat pendukung yang berkemampuan 3D, dan aplikasi-aplikasi 3D. Sebagai fenomena yang terjadi saat ini, smartphone, tablet, dan perangkat mobile lainnya sudah melampaui nilai penjualan PC. Bersamaan dengan semakin populernya video 3D dan diaplikasikan ke perangkat mobile tersebut, mengakibatkan kebutuhan akan penyimpanan, transmisi data, dan tampilan membutuhkan pengkodean yang efisien. High Efficiency Video Coding (HEVC) adalah teknik pengkodean video yang telah didesain menjadi standar untuk banyak aplikasi video dan memiliki kehandalan yang cukup signifikan dari generasi pendahulunya seperti teknik pengkodean H.264. Meskipun HEVC memiliki pengkodean yang sangat efiesien, namun disamping itu memerlukan beban prosesor yang berat dan menjalankan beban yang paralel pada saat pengkodean data yang berisi video. Untuk meningkatkan kehandalan dalam proses encoder, salah satunya dapat dilakukan dengan mengimplementasikan kode HEVC ke Zynq 7000 AP SoC. Diaplikasikan dalam tiga desain yaitu pertama dengan mengimplementasikan kedalam Zynq PS sebagai operasi standalone. Kedua yaitu dengan mengimplementasikan HEVC encoder dalam hardware/software co-design. Dan ketiga, implementasi code HEVC ke Zynq PL, tanpa PS. Dalam implementasi ini digunakan perangkat Xilinx Vivado HLS untuk mengembangkan kode yang dibutuhkan. Nilai hasil yang akan didapatkan adalah waktu yang dibutuhkan untuk pengkodean, PSNR, dan ukuran file hasil pengkodean kemudian akan dibandingkan antara kinerja PC berbasis Linux dengan FPGA Xilinx Zynq-7000. ======================================================================================================================== Consumer demand for new multimedia technologies and more reliable, drove the industry to improve services in the field of entertainment marketing, so that the estuary encourage the popularization of 3D video content, supporting devices 3D capabilities, and 3D applications. As a phenomenon that occurs at this time, smartphones, tablets, and other mobile devices has surpassed the value of PC sales. Along with the growing popularity of 3D video and be applied to the mobile device, resulting in the need for storage, data transmission, and display requires an efficient coding. High Efficiency Video Coding (HEVC) is a video coding technique that has been designed to become the standard for many video applications and has the reliability significantly from the preceding generation such as H.264 coding techniques. Although HEVC has very efiesien coding, but besides that it requires a heavy processor load and run parallel load at the time of encoding data containing the video. To improve reliability in the process of encoder, one of which can be done by implementing a code HEVC to Zynq 7000 AP SoC. Applied in three designs into Zynq first to implement PS as a standalone operation. The second is to implement HEVC encoder in hardware / software co-design. And third, the implementation code HEVC to Zynq PL, without PS. In this implementation Xilinx device is used Vivado HLS to develop the code needed. The value of the results to be obtained is the time required for video encoding, PSNR, and encoded file size that will be compared between the performance of Linux-based PCs with Xilinx Zynq-7000 FPGA

Optimization and Mining Methods for Effective Real-Time Embedded Systems

L’Internet des objets (IoT) est le réseau d’objets interdépendants, comme les voitures autonomes, les appareils électroménagers, les téléphones intelligents et d’autres systèmes embarqués. Ces systèmes embarqués combinent le matériel, le logiciel et la connection réseau permettant le traitement de données à l’aide des puissants centres de données de l’informatique nuagique. Cependant, la croissance exponentielle des applications de l’IoT a remodelé notre croyance sur l’informatique nuagique, et des certitudes durables sur ses capacités ont dû être mises à jour. De nos jours, l’informatique nuagique centralisé et classique rencontre plusieurs défis, tels que la latence du trafic, le temps de réponse et la confidentialité des données. Alors, la tendance dans le traitement des données générées par les dispositifs embarqués interconnectés consiste à faire plus de calcul au niveau du dispositif au bord du réseau. Cette possibilité de faire du traitement local aide à réduire la latence pour les applications temps réel présentant des fortes contraintes temporelles. Aussi, ça permet d’améliorer le traitement des quantités massives de données générées par ces périphériques. Réussir cette transition nécessite la conception de systèmes embarqués de haute performance en explorant efficacement les alternatives de conception (i.e. Exploration efficace de l’espace des solutions), en optimisant la topologie de déploiement des applications temps réel sur des architectures multi-processeurs (i.e. la façon dont le logiciel utilise le matériel) , et des algorithme d’exploration permettant un fonctionnement plus intelligent de ces dispositifs. Des efforts de recherche récents ont conduit à diverses approches automatisées facilitant la conception et l’amélioration du fonctionnement des système embarqués. Cependant, ces techniques existantes présentent plusieurs défis majeurs. Ces défis sont fortement présents sur les systèmes embarqués temps réel. Quatre des principaux défis sont : (1) Le manque de techniques d’exploration de données en ligne permettant l’amélioration des performances des systèmes embarqués. (2) L’utilisation inefficace des ressources informatiques des systèmes multiprocesseurs lors du déploiement de logiciels là dessus ; (3) L’exploration pseudo-aléatoire de l’espace des solutions (4) La sélection de la configuration appropriée à partir de la listes des solutions optimales obtenue.----------ABSTRACT: The Internet of things (IoT) is the network of interrelated devices or objects, such as selfdriving cars, home appliances, smart-phones and other embedded computing systems. It combines hardware, software, and network connectivity enabling data processing using powerful cloud data centers. However, the exponential rise of IoT applications reshaped our belief on the cloud computing, and long-lasting certainties about its capabilities had to be updated. The classical centralized cloud computing is encountering several challenges, such as traffic latency, response time, and data privacy. Thus, the trend in the processing of the generated data of IoT inter-connected embedded devices has shifted towards doing more computation closer to the device in the edge of the network. This possibility to do on-device processing helps to reduce latency for critical real-time applications and better processing of the massive amounts of data being generated by the these devices. Succeeding this transition towards the edge computing requires the design of high-performance embedded systems by efficiently exploring design alternatives (i.e. efficient Design Space Exploration), optimizing the deployment topology of multi-processor based real-time embedded systems (i.e. the way the software utilizes the hardware), and light mining techniques enabling smarter functioning of these devices. Recent research efforts on embedded systems have led to various automated approaches facilitating the design and the improvement of their functioning. However, existing methods and techniques present several major challenges. These challenges are more relevant when it comes to real-time embedded systems. Four of the main challenges are : (1) The lack of online data mining techniques that can enhance embedded computing systems functioning on the fly ; (2) The inefficient usage of computing resources of multi-processor systems when deploying software on ; (3) The pseudo-random exploration of the design space ; (4) The selection of the suitable implementation after performing the otimization process

Finding, Measuring, and Reducing Inefficiencies in Contemporary Computer Systems

Computer systems have become increasingly diverse and specialized in recent years. This complexity supports a wide range of new computing uses and users, but is not without cost: it has become difficult to maintain the efficiency of contemporary general purpose computing systems. Computing inefficiencies, which include nonoptimal runtimes, excessive energy use, and limits to scalability, are a serious problem that can result in an inability to apply computing to solve the world's most important problems. Beyond the complexity and vast diversity of modern computing platforms and applications, a number of factors make improving general purpose efficiency challenging, including the requirement that multiple levels of the computer system stack be examined, that legacy hardware devices and software may stand in the way of achieving efficiency, and the need to balance efficiency with reusability, programmability, security, and other goals. This dissertation presents five case studies, each demonstrating different ways in which the measurement of emerging systems can provide actionable advice to help keep general purpose computing efficient. The first of the five case studies is Parallel Block Vectors, a new profiling method for understanding parallel programs with a fine-grained, code-centric perspective aids in both future hardware design and in optimizing software to map better to existing hardware. Second is a project that defines a new way of measuring application interference on a datacenter's worth of chip-multiprocessors, leading to improved scheduling where applications can more effectively utilize available hardware resources. Next is a project that uses the GT-Pin tool to define a method for accelerating the simulation of GPGPUs, ultimately allowing for the development of future hardware with fewer inefficiencies. The fourth project is an experimental energy survey that compares and combines the latest energy efficiency solutions at different levels of the stack to properly evaluate the state of the art and to find paths forward for future energy efficiency research. The final project presented is NRG-Loops, a language extension that allows programs to measure and intelligently adapt their own power and energy use

Journal of Telecommunications and Information Technology, 2010, nr 2

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