26,472 research outputs found
Operating System Kernels on Multi-core Architectures
Operating System (OS) kernels have been under research and development for decades, mainly assuming single processor and distributed hardware systems.
With the recent rise of multi-core chips that may incorporate a network on chip (NoC), new challenges have appeared that were not considered before.
Given that a complete multi-core system that works on a single system on chip (SoC) is now the normal case, different cores on a single SoC may
share other physical resources and data. This new sharing scheme on a SoC affects crucial aspects of an overall system like correctness, performance,
predictability, scalability and security. Both hardware and OSs to flexibly cooperate in order to provide
solutions for such challenges.
SoC mimics the internet somehow now, with different cores acting as computer nodes, and the network medium is given in an advanced digital fabrics like buses or NoCs, that are
a current research area. However, OSs are still assuming some (hardware) features like single physical memory and memory sharing for inter-process communication, page-based protection, cache operations, even when evolving from uniprocessor to multi-core processors.
Such features not only may degrade performance and other system aspects, but also
some of them make no sense for a multi-core SoC, and introduce some barriers and limitations. While new OS research is considering different kernel designs
to cope up with multi-core systems, they are still limited by the current commercial hardware architectures.
The objective of this thesis is to assess different kernel designs and implementations on multi-core hardware architectures.
Part of the contributions of the thesis is porting
RTEMS (RTOS) and seL4 microkernel to Epiphany and RISC-V hardware architectures respectively, trading-off the design and implementation decisions. This hands-on experience gave a better understanding of the real-world challenges regarding kernel designs and implementations
The communication processor of TUMULT-64
Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type, distributed memory, message passing, high performance, real-time and fault tolerant. A distributed real-time operating system has been realized, consisting of a multi-tasking kernel per node, inter process communication via typed messages and a distributed file system. In this paper first a brief description of the system is given, after that the architecture of the communication processor will be discussed. Reduction of the communication overhead due to message passing will be emphasized.\ud
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Embedding Multi-Task Address-Event- Representation Computation
Address-Event-Representation, AER, is a communication protocol that is
intended to transfer neuronal spikes between bioinspired chips. There are
several AER tools to help to develop and test AER based systems, which may
consist of a hierarchical structure with several chips that transmit spikes
among them in real-time, while performing some processing. Although these
tools reach very high bandwidth at the AER communication level, they require
the use of a personal computer to allow the higher level processing of the
event information. We propose the use of an embedded platform based on a
multi-task operating system to allow both, the AER communication and
processing without the requirement of either a laptop or a computer. In this
paper, we present and study the performance of an embedded multi-task AER
tool, connecting and programming it for processing Address-Event
information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
MGSim - Simulation tools for multi-core processor architectures
MGSim is an open source discrete event simulator for on-chip hardware
components, developed at the University of Amsterdam. It is intended to be a
research and teaching vehicle to study the fine-grained hardware/software
interactions on many-core and hardware multithreaded processors. It includes
support for core models with different instruction sets, a configurable
multi-core interconnect, multiple configurable cache and memory models, a
dedicated I/O subsystem, and comprehensive monitoring and interaction
facilities. The default model configuration shipped with MGSim implements
Microgrids, a many-core architecture with hardware concurrency management.
MGSim is furthermore written mostly in C++ and uses object classes to represent
chip components. It is optimized for architecture models that can be described
as process networks.Comment: 33 pages, 22 figures, 4 listings, 2 table
Spike Processing on an Embedded Multi-task Computer: Image Reconstruction
There is an emerging philosophy, called Neuro-informatics, contained
in the Artificial Intelligence field, that aims to emulate how living beings do tasks
such as taking a decision based on the interpretation of an image by emulating spiking
neurons into VLSI designs and, therefore, trying to re-create the human brain at
its highest level. Address-Event-Representation (AER) is a communication protocol
that has embedded part of the processing. It is intended to transfer spikes between
bioinspired chips. An AER based system may consist of a hierarchical structure with
several chips that transmit spikes among them in real-time, while performing some
processing. There are several AER tools to help to develop and test AER based systems.
These tools require the use of a computer to allow the higher level processing of
the event information, reaching very high bandwidth at the AER communication level.
We propose the use of an embedded platform based on a multi-task operating system
to allow both, the AER communication and processing without the requirement of either
a laptop or a computer. In this paper, we present and study the performance of a
new philosophy of a frame-grabber AER tool based on a multi-task environment. This
embedded platform is based on the Intel XScale processor which is governed by an
embedded GNU/Linux system. We have connected and programmed it for processing
Address-Event information from a spiking generator.Ministerio de Educación y Ciencia TEC2006-11730-C03-0
A Comprehensive Experimental Comparison of Event Driven and Multi-Threaded Sensor Node Operating Systems
The capabilities of a sensor network are strongly influenced by the operating system used on the sensor nodes. In general, two different sensor network operating system types are currently considered: event driven and multi-threaded. It is commonly assumed that event driven operating systems are more suited to sensor networks as they use less memory and processing resources. However, if factors other than resource usage are considered important, a multi-threaded system might be preferred. This paper compares the resource needs of multi-threaded and event driven sensor network operating systems. The resources considered are memory usage and power consumption. Additionally, the event handling capabilities of event driven and multi-threaded operating systems are analyzed and compared. The results presented in this paper show that for a number of application areas a thread-based sensor network operating system is feasible and preferable
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