A Survey of Lightweight Cryptosystems for Smart Home Devices

A Smart Home uses interconnected network technology to monitor the environment, control the various physical appliances, and communicate with each other in a close environment. A typical smart home is made up of a security system, intercommunication system, lighting system, and ventilation system.  Data security schemes for smart homes are ineffective due to inefficiency cryptosystems, high energy consumption, and low exchange security. Traditional cryptosystems are less-applicable because of their large block size, large key size, and complex rounds. This paper conducts a review of smart homes, and adopts Ultra-Sooner Lightweight Cryptography to secure home door. It provides extensive background of cryptography, forms of cryptography as associated issues and strengths, current trends, smart home door system design, and future works suggestions. Specifically, there are prospects of utilizing XORed lightweight cryptosystem for developing encryption and decryption algorithms in smart home devices. The Substitution Permutation Network, and Feistel Network cryptographic primitives were most advanced forms of cipher operations with security guarantees. Therefore, better security, memory and energy efficiency can be obtained with lightweight ciphers in smart home devices when compared to existing solutions. In the subsequent studies, a blockchain-based lightweight cryptography can be the next springboard in attaining the most advanced security for smart home systems and their appliances.     &nbsp

Pipelined Asynchronous High Level Synthesis for General Programs

High-level synthesis (HLS) translates algorithms from software programming language into hardware. We use the dataflow HLS methodology to translate programs into asynchronous circuits by implementing programs using asynchronous dataflow elements as hardware building blocks. We extend the prior work in dataflow synthesis in the following aspects:i) we propose Fluid to synthesize pipelined dataflow circuits for real-world programs with complex control flows, which are not supported in the previous work; ii) we propose PipeLink to permit pipelined access to shared resources in the dataflow circuit. Dataflow circuit results in distributed control and an implicitly pipelined implementation. However, resource sharing in the presence of pipelining is challenging in this context due to the absence of a global scheduler. Traditional solutions to this problem impose restrictions on pipelining to guarantee mutually exclusive access to the shared resource, but PipeLink removes such restrictions and can generate pipelined asynchronous dataflow circuits for shared function calls, pipelined memory accesses and function pointers; iii) we apply several dataflow optimizations to improve the quality of the synthesized dataflow circuits; iv) we implement our system (Fluid + PipeLink) on the LLVM compiler framework, which allows us to take advantage of the optimization efforts from the compiler community; v) we compare our system with a widely-used academic HLS tool and two commercial HLS tools. Compared to commercial (academic) HLS tools, our system results in 12X (20X) reduction in energy, 1.29X (1.64X) improvement in throughput, 1.27X (1.61X) improvement in latency at a cost of 2.4X (1.61X) increase in the area

Physics-based surface energy model optimization for water bodies in cold climates using visible and calibrated thermal infrared imagery

When tasked with accurately modeling a water body in a cold climate environment, the complexity of the system being simulated and the numerous parameters affecting the observable outcome pose an arduous task for any modeling effort. The task is increasingly complicated when the body of water is serving as a cooling pond for a power plant and can become partially frozen. The introduction of a heat effluent into the water creates a highly dynamic system whose physical state is not only reactionary to the surrounding environmental conditions, but the industrial facility\u27s operating parameters as well. Both calibrated thermal and visible imagery offer a powerful and unique source of validation data for these hydrodynamic modeling codes when trying to simulate these industrial processes in cold climates. This work presents an approach which uses an evolutionary optimization algorithm to drive the inputs of a hydrodynamic modeling code simulating a power plant cooling pond through imagery validation. The result of this process is an optimized set of functional parameters to the hydrodynamic model that best simulates the observed conditions. While applied to a hydrodynamic code for this work, the process created introduces a unique infrastructure for solving multi-dimensional, multi-system problem sets in a modular and evolutionary framework

Hardware implementation of intelligent systems

interior, interior vie

Regular Datapaths on Field-Programmable Gate Arrays

Field-Programmable Gate Arrays (FPGAs) are a recent kind of programmable logic device. They allow the implementation of integrated digital electronic circuits without requiring the complex optical, chemical and mechanical processes used in a conventional chip fabrication. FPGAs can be embedded in traditional system designflows to perform prototyping and emulation tasks. In addition, they also enable novel applications such as configurable computers with hardware dynamically adaptable to a specific problem. The growing chip capacity now allows even the implementation of CPUs and DSPs on single FPGAs. However, current design automation tools trace their roots to times of very limited FPGA sizes, and are primarily optimized for the implementation of random glue logic. The wide datapaths common to CPUs and DSPs are only processed with reduced performance. This thesis presents Structured Design Implementation (SDI), a suite of specialized tools coordinated by a common strategy, which aims to efficiently map even larger regular datapaths to FPGAs. In all steps, regularity is preserved whenever possible, or restored after disruptive operations were required. The circuits are composed from parametrizable modules providing a variety of logical, arithmetical and storage functions. For each module, multiple target FPGA-specific implementation alternatives may be generated in both gatelevel netlist and layout views. A floorplanner based on a genetic algorithm is then used to simultaneously choose an actual implementation from the set of alternatives for each module, and to arrange the selected module implementations in a linear placement. The floorplanning operation optimizes for short routing delays, high routability, and fit into the target FPGA.Field-Programmable Gate-Arrays (FPGAs) sind eine noch junge Art von programmierbaren Logikbausteinen. Sie erlauben die Implementierung von integrierten Digitalschaltungen ohne die komplizierten optischen, chemischen und mechanischen Prozesse, die normalerweise für die Chipfertigung erforderlich sind. FPGAs können im Rahmen konventioneller Entwurfsmethoden zu Emulationszwecken und Prototyp-Aufbauten herangezogen werden. Sie erlauben aber auch völlig neue Anwendungen wie rekonfigurierbare Computer, deren Hardware dynamisch an ein spezielles Problem angepaßt werden kann. Die gewachsene Chip-Kapazität erlaubt nun sogar die Implementierung von CPUs und digitalen Signalprozessoren (DSPs) auf einem einzelnen FPGA. Die Leistungsfähigkeit der entstandenen Schaltungen wird jedoch durch die zur Zeit erhältlichen CAD-Werkzeuge limitiert, da diese noch auf stark beschränkte FPGA-Größen ausgerichtet sind und primär der platzsparenden Verarbeitung unregelmäßiger Logik dienen. Die breiten Datenpfade in Bit-Slice-Struktur, die den Kern vieler CPUs und DSPs darstellen, werden nur suboptimal behandelt. Diese Arbeit stellt Structured Design Implementation (SDI) vor, ein System von spezialisierten CAD-Werkzeugen, die auch größere reguläre Datenpfade effizient auf FPGAs abbilden. In allen Verarbeitungsschritten wird dabei die bestehende Regularität soweit wie möglich erhalten oder nach regularitätsvernichtenden Operationen wiederhergestellt. Zur Schaltungseingabe steht eine Bibliothek von allgemeinen Modulen aus den Bereichen Logik, Arithmetik und Speicherung bereit. Diese können durch Belegung verschiedener Parameter wie Bit-Breiten und Datentypen an aktuelle Anforderungen angepaßt werden