Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

Phase Synthesis Using Coupled Phase-Locked Loops

Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems. This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation

Lookup-Table-Based Background Linearization for VCO-Based ADCs

Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower VDD environment. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The major obstacle in the VCO-based technique is linearizing the VCO voltage-to-frequency characteristic. Achieving signal-to-noise (SNR) performance better than -40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. A further challenge is implementing calibration without degrading energy efficiency performance. This thesis project discusses a complete design of a 10 bit three stage ring VCO-based ADC. A lookup-table (LUT) digital correction technique enabled by the Split ADC calibration approach is presented suitable for linearization of the ADC. An improvement in the calibration algorithm is introduced to ensure LUT continuity. Measured results for a 10 bit 48.8-kSps ADC show INL improvement of 10X after calibration convergence

Ring-oscillator with multiple transconductors for linear analog-to-digital conversion

This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.This research was funded by Project TEC2017-82653-R, Spain

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Advanced modulation technology development for earth station demodulator applications

The purpose of this contract was to develop a high rate (200 Mbps), bandwidth efficient, modulation format using low cost hardware, in 1990's technology. The modulation format chosen is 16-ary continuous phase frequency shift keying (CPFSK). The implementation of the modulation format uses a unique combination of a limiter/discriminator followed by an accumulator to determine transmitted phase. An important feature of the modulation scheme is the way coding is applied to efficiently gain back the performance lost by the close spacing of the phase points

A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB