A 4-mode reconfigurable low noise amplifier for implantable neural recording channels

In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by circuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.Office of Naval Research (USA) N00014-14-1-0355Junta de Andalucía TIC 233

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 ??m complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.ope

A True 1V 1µW Biomedical Front End with Reconfigurable ADC for Self powered Smarter IoT Healthcare Systems

This work proposes an ultralow power highly linear analog front-end (AFE) with an input dynamic range from 200μVpp to 20mVpp. The system consists of a signal conditioning instrumentation amplifier (IA), two programmable gain amplifiers (PGA), a mixed signal automatic gain control (AGC), two sample and hold (S/H), a 10 bit successive approximation register (SAR) analog to digital converter (ADC), and a ΣΔ modulator with 10 bit effective number of bits (ENOB). A highly linear capacitively-coupled IA is achieved by increasing its feedback factor. Moreover, a transconductance (gm) cancellation technique is proposed for achieving a high common mode rejection ratio (CMRR). The conditioned signal is digitized using a SAR ADC for an input range of 200μVpp to 2mVpp, and, an opamp-shared ΣΔ ADC for an input range of 2mVpp to 20mVpp. The selection between the two ADCs is done by the AGC. The full system is designed using 1V supply in UMC 0.18μm CMOS technology. The AFE (IA and the two PGAs) achieves an overall linearity of more than 12 bits, for an input range of 200μVpp to 20mVpp while consuming 300nW with a bandwidth of 0.05 - 250Hz. The power consumption of the SAR ADC is 40nW while operating at a sampling frequency of 1KHz. The ΣΔ ADC consumes 300nW at a sampling frequency of 32KHz with an OSR of 32. The proposed system is intended to be powered by an energy scavenging circuit without compromising its own performance. The system was successfully tested for an ECG signal obtained from PTB database

Low Power Analog Front End for ExG Acquisition with Automatic Gain Control and Analog Classification

Cardiovascular diseases have been known to cause large number of deaths globally. For prevention and early detection of these diseases, continuous monitoring of ecg signals is required. With recent advances in IC technology, implantable ICs have seen the light of the day. Considering the im-plantable devices, power consumed by the system needs to be as less as possible without sacrificing the performance of the readout circuit

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2nd order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices

Noise Efficient Integrated Amplifier Designs for Biomedical Applications

The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2

A versatile wearable based on reconfigurable hardware for biomedical measurements

In this work a versatile hardware platform based on reconfigurable devices is presented. This platform it intended for the acquisition of multiple biosignals, only requiring a reconfiguration to switch applications. This prototype has been combined with graphene-based, flexible electrodes to cover the application to different biosignals presented in this paper, which are electrocardiogram, electrooculogram and electromyogram. The features of this system provide to the user and to medical personnel a complete set of diagnosis tools, available both at home and hospitals, to be used as a triage tool and for remote patient monitoring. Additionally, an Android application has been developed for signal processing and data presentation to the user. The results obtained demonstrate the wide range of possibilities in portable/wearable applications of the combination of reconfigurable devices and flexible electronics, especially for the remote monitoring of patients using multiple biosignals of interest. The versatility of this device makes it a complete set of monitoring tools integrated in a reduced size device

Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring

This paper describes a mixed-signal ECG system for personalized and remote cardiac health monitoring. The novelty of this work is four-fold. Firstly, a low power analog front end with an efficient automatic gain control mechanism, maintaining the input of the ADC to a level rendering optimum SNR and the enhanced recyclic folded cascode opamp used as an integrator for ADC. Secondly, a novel on-the-fly PQRST Boundary Detection (BD) methodology is formulated for finding the boundaries in continuous ECG signal. Thirdly, a novel low-complexity ECG feature extraction architecture is designed by reusing the same module present in the proposed BD methodology. Fourthly, the system is having the capability to reconfigure the proposed Low power ADC for low (8 bits) and high (12 bits) resolution with the use of the feedback signal obtained from the digital block when it is in processing. The proposed system has been tested and validated on patient’s data from PTBDB, CSEDB and in-house IIT Hyderabad DB (IITHDB) and we have achieved an accuracy of 99% upon testing on various normal and abnormal ECG signals. The whole system is implemented in 180 nm technology resulting in 9.47W (@ 1 MHz) power consumption and occupying 1.74mm2 silicon area

New Architectures and Circuits for Pushing the Dynamic Range and Multiplexing Boundaries of CMOS-Integrated Sensors

Over the last decades, CMOS-integrated sensors have made impressive progress in performance, form-factor, and energy-efficiency for various applications such as imaging, physical/chemical sensing, bio/health monitoring. In the era of the artificial intelligence (AI) and the internet-of-things (IoT), such CMOS-integrated sensors are essential for massive and comprehensive data acquisition, where sensing range (or dynamic range), signal fidelity (or signal-to-noise ratio), and data throughput are key factors. Towards pushing the boundaries of such sensing capabilities, in this dissertation, novel sensing architectures are presented with energy/area-efficient circuit design techniques for multi-channel CMOS optical sensors and neural interfaces. The first topic is a fully-integrated, wide linear dynamic range optical sensor array combining linear and single-photon avalanche diode operation within each pixel. A pulse-counting readout scheme provides in-pixel digitization in an area-efficient manner for both operation modes, enabling fully parallel measurement across the array. The proposed dual-mode optical sensor array alternately requires high-voltage(10-20 V) and low-voltage supply (2-5 V) for reverse bias of the photodiodes, which is provided by a reconfigurable, closed-loop high-voltage charge pump in the same substrate. An 8 x 8 array architecture along with the dual-mode bias generator is fabricated in a general purpose 180 nm CMOS process and demonstrates 129 dB dynamic range while maintaining linear photoresponse operating with a dual-mode frame rate of 20 Hz. The second topic is a new approach for applying code-division multiplexing (CDM) to current-mode and voltage-mode sensor arrays with analog-domain orthogonal encoding directly in a shared, single analog-front-end circuit, which enables simultaneous readout for multiple sensors. The approach is applied to a 8 x 16 array of CMOS-integrated photodetectors and implemented in a general purpose 180 nm CMOS process, where the 16 channel CDM-based oversampling readout achieves an SNR improvement of more than 12 dB compared with time-division multiplexing at the same sampling rate. In addition, a CDM-based neural recording architecture is presented, which offers a significant tolerance to interference that can be injected through long cables