A fully-integrated 1.8-V, 2.8-W, 1.9-GHz, CMOS power amplifier

This paper demonstrated the first 2-stage, 2.8W, 1.8V, 1.9GHz fully-integrated DAT power amplifier with 50Ω input and output matching using 0.18μm CMOS transistors. It has a small-signal gain of 27dB. The amplifier provides 2.8W of power into a 50Ω load with a PAE of 50%

Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Cross-polarized photon-pair generation and bi-chromatically pumped optical parametric oscillation on a chip

Nonlinear optical processes are one of the most important tools in modern optics with a broad spectrum of applications in, for example, frequency conversion, spectroscopy, signal processing and quantum optics. For practical and ultimately widespread implementation, on-chip devices compatible with electronic integrated circuit technology offer great advantages in terms of low cost, small footprint, high performance and low energy consumption. While many on-chip key components have been realized, to date polarization has not been fully exploited as a degree of freedom for integrated nonlinear devices. In particular, frequency conversion based on orthogonally polarized beams has not yet been demonstrated on chip. Here we show frequency mixing between orthogonal polarization modes in a compact integrated microring resonator and demonstrate a bi-chromatically pumped optical parametric oscillator. Operating the device above and below threshold, we directly generate orthogonally polarized beams, as well as photon pairs, respectively, that can find applications, for example, in optical communication and quantum optics

Integrated frequency comb source of heralded single photons

We report an integrated photon pair source based on a CMOS-compatible microring resonator that generates multiple, simultaneous, and independent photon pairs at different wavelengths in a frequency comb compatible with fiber communication wavelength division multiplexing channels (200 GHz channel separation) and with a linewidth that is compatible with quantum memories (110 MHz). It operates in a self-locked pump configuration, avoiding the need for active stabilization, making it extremely robust even at very low power levels

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​In this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.Peer reviewe

Design of linear transmitters for wireless applications

Wireless standards for high data-rate communications typically employ complex modulation schemes that have large peak-to-average power ratios (PAPR), along with a significant bandwidth requirement. Transmitters for such applications often employ off-chip power amplifiers (PAs), that are typically operated in back-off, such that the peak output power is less than the output 1-dB compression point (P1dB), in order to minimize distortion. In mobile systems, architectures that can enhance the linearity of the transmit chain are highly attractive since these can reduce the PA's back-off requirement, which helps to enhance efficiency. In this dissertation, linearization techniques for mobile transmitters are explored. A Cartesian feedback-feedforward transmitter is proposed for linearity enhancement. The transmit path in the architecture is placed in a Cartesian feedback loop. The feedback error signal is applied to a Cartesian feedforward path for further linearity improvement. Linearity of the feedback-feedforward system is analyzed by using a Volterra series representation. System simulations using two-tone signals and modulated signals are also presented and are used to verify the linearity enhancement provided by the proposed architecture. A prototype transmitter IC that employs the Cartesian feedback-feedforward approach is implemented in a 0.13 μm CMOS process. Design considerations for critical transmitter circuits are discussed. A proof-of-concept Cartesian feedback-feedforward architecture that includes the prototype IC and external components is demonstrated. The implementation allows for a 8.7 dB improvement in the adjacent channel leakage ratio (ACLR), compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16-QAM LTE signal with 1.4 MHz bandwidth. The linearity of the Cartesian feedback-feedforward system is found to depend primarily on the loop gain of the Cartesian feedback and the linearity of the Cartesian feedforward path, which introduces a trade-off with power consumption. To enhance the linearity of the Cartesian feedback-feedforward transmitter even further within the Cartesian feedback loop, two modified Cartesian feedback-feedforward architectures are explored. System simulations show that both modified configurations can help to enhance linearity compared to the above Cartesian feedback-feedforward transmitter.Electrical and Computer Engineerin

Mid-Infrared nonlinear silicon photonics

Recently there has been a growing interest in mid-infrared (mid-IR) photonic technology with a wavelength of operation approximately from 2-14 mu m. Among several established mid-IR photonic platforms, silicon nanophotonic platform could potentially offer ultra-compact, and monolithically integrated mid-IR photonic devices and device arrays, which could have board impact in the mid-IR technology, such as molecular spectroscopy, and imaging. At room temperature, silicon has a bandgap similar to 1.12 eV resulting in vanishing two-photon absorption (TPA) for mid-IR wavelengths beyond 2.2 mu m, which, coupled with silicon's large nonlinear index of refraction and its strong waveguide optical confinement, enables efficient nonlinear processes in the mid-IR. By taking advantage of these nonlinear processes and judicious dispersion engineering in silicon waveguides, we have recently demonstrated a handful of silicon mid-IR nonlinear components, including optical parametric amplifiers (OPA), broadband sources, and a wavelength translator. Silicon nanophotonic waveguide's anomalous dispersion design, providing four-wave-mixing (FWM) phase-matching, has enabled the first demonstration of silicon mid-IR optical parametric amplifier (OPA) with a net off-chip gain exceeding 13 dB. In addition, reduction of propagation losses and balanced second and fourth order waveguide dispersion design led to an OPA with an extremely broadband gain spectrum from 1.9-2.5 mu m and > 50 dB parametric gain, upon which several novel silicon mid-IR light sources were built, including a mid-IR optical parametric oscillator, and a supercontinuum source. Finally, a mid-IR wavelength translation device, capable of translating signals near 2.4 mu m to the telecom-band near 1.6 mu m with simultaneous 19 dB gain, was demonstrated

Design of a 10GHz RF power amplifier in 130nm CMOS technology based on Wilkinson combiner methodology

There is a growing demand today to design and fabricate RF power amplifiers at high frequencies above 5GHz that can directly drive a 50Ω antenna with sufficiently high transmission power to meet the needs of various wireless communication applications. This has typically been done by using GaN or other III-V technologies to build the power amplifier transistor, in order to allow for the use of much higher power supply voltages, than are used in today’s silicon technologies. For example, a 5W GaN power amplifier at 5GHz would typically make use of a VDD of 5V to 10V, and would be done as a discrete device on a separate module from the RF analog circuitry built out of silicon. With the continuing evolution of Moore’s Law, silicon technologies in use today for high frequency wireless communications typically are using VDD of 1.5V or less. There is a desire, however, in many wireless applications to be able to place the RF power amplifier on the same silicon chip as all the other RF/analog IC circuitry, in order to save chip fabrication cost. Consequently, research in improved methods of RF power amplifier design in silicon technology is being done in many IC design laboratories in order to increase the RF power output of power amplifiers built in silicon. This MS Thesis proposes the complete design of a four channel RF power amplifier by using the Wilkinson combiner with 27dBm output power. All the circuits are designed and implemented based on the Global Foundries 130nm SiGe BiCMOS technology and design kit at a frequency of 10GHz with a VDD = 1.5V, to provide 0.5W of RF output signal power into a 50Ω antenna