Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard

This is the accepted manuscript version of the following article: Xiaofeng He, et al., “A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61(10): 763-767, August 2014. The final published version is available at: http://ieeexplore.ieee.org/document/6871304/ © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The design of a 14-mW receiver without phase-locked loop for the Chinese electronic toll collection (ETC) system in a standard 0.18-μm CMOS process is presented in this brief. Since the previously published work was mainly based on vehicle-powered systems, low power consumption was not the primary goal of such a system. In contrast, the presented system is designed for a battery-powered system. Utilizing the presented receiver architecture, the entire receiver only consumes 7.8 mA, at the supply voltage of 1.8 V, which indicates a power saving of at least 38% compared with other state-of-the-art designs for the same application. To verify the performance, the bit error rate is measured to be better than 10-6, which well satisfies the Chinese ETC standard. Moreover, the sensitivity of the designed receiver can be readjusted to -50 dBm, which is required by the standard.Peer reviewe

A power efficient frequency divider with 55 GHz self-oscillating frequency in SiGe BiCMOS

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology isreported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimizationof layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz anda self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This resultsin high efficiency with respect to other static frequency dividers in BiCMOS technology presentedin the literature. The divider topology does not use inductors, thus optimizing the area footprint:the divider core occupies 60×65μm2on silicon

Millimeter-Wave Concurrent Dual-Band BiCMOS RFICs for Radar and Communication RF Front-End

The recent advancement in silicon-based technologies has offered the opportunity for the development of highly-integrated circuits and systems in the millimeter-wave frequency regime. In particular, the demand for high performance multi-band multi-mode radar and communication systems built on silicon-based technologies has been increased dramatically for both military and commercial applications. This dissertation presents the design and implementation of advanced millimeter-wave front-end circuits in SiGe BiCMOS process including a transmit/receive switch module with integrated calibration function, low noise amplifier, and power amplifier for millimeter-wave concurrent dual-band dual-polarization radars and communication systems. The proposed circuits designed for the concurrent dual-band dual-polarization radars and communication systems were fabricated using 0.18-μm BiCMOS process resulting in novel circuit architectures for concurrent multi-band operation. The developed concurrent dual-band circuits fabricated on 0.18-μm BiCMOS process include the T/R/Calibration switch module for digital beam forming array system at 24.5/35 GHz, concurrent dual-band low noise amplifiers at 44/60 GHz, and concurrent dual-band power amplifier at 44/60 GHz. With having all the design frequencies closely spaced to each other showing the frequency ratio below 1.43, the designed circuits provided the integrated dual-band filtering function with Q-enhanced frequency responses. Inspired by the composite right/left- handed metamaterial transmission line approaches, the integrated Q-enhanced filtering sub-circuits provided unprecedented dual-band filtering capability. The new concurrent dual-band dual-mode circuits and system architecture can provide enhanced radar and communication system performance with extended coverage, better image synthesis and target locating by the enhanced diversity. The circuit level hardware research conducted in this dissertation is expected to contribute to enhance the performance of multi-band multi-mode imaging, sensing, and communication array systems

Wideband integrated circuits for optical communication systems

The exponential growth of internet traffic drives datacenters to constantly improvetheir capacity. Several research and industrial organizations are aiming towardsTbps Ethernet and beyond, which brings new challenges to the field of high-speedbroadband electronic circuit design. With datacenters rapidly becoming significantenergy consumers on the global scale, the energy efficiency of the optical interconnecttransceivers takes a primary role in the development of novel systems. Furthermore,wideband optical links are finding application inside very high throughput satellite(V/HTS) payloads used in the ever-expanding cloud of telecommunication satellites,enabled by the maturity of the existing fiber based optical links and the hightechnology readiness level of radiation hardened integrated circuit processes. Thereare several additional challenges unique in the design of a wideband optical system.The overall system noise must be optimized for the specific application, modulationscheme, PD and laser characteristics. Most state-of-the-art wideband circuits are builton high-end semiconductor SiGe and InP technologies. However, each technologydemands specific design decisions to be made in order to get low noise, high energyefficiency and adequate bandwidth. In order to overcome the frequency limitationsof the optoelectronic components, bandwidth enhancement and channel equalizationtechniques are used. In this work various blocks of optical communication systems aredesigned attempting to tackle some of the aforementioned challenges. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback,are designed and measured, utilizing a state-of-the-art 130 nm InP DHBT technology.A modular equalizer block built in 130 nm SiGe HBT technology is presented. Threeultra-wideband traveling wave amplifiers, a 4-cell, a single cell and a matrix single-stage, are designed in a 250 nm InP DHBT process to test the limits of distributedamplification. A differential VCSEL driver circuit is designed and integrated in a4x 28 Gbps transceiver system for intra-satellite optical communications based in arad-hard 130nm SiGe process

Analysis and design of a high power millimeter-wave power amplifier in a SiGe BiCMOS technology

Our current society is characterized by an ever increasing need for bandwidth leading towards the exploration of new parts of the electromagnetic spectrum for data transmission. This results in a rising interest and development of millimeter-wave (mm-wave) circuits which hold the promise of short range multi-gigabit wireless transmissions at 60GHz. These relatively new applications are to co-exist with more established mm-wave consumer products including satellite systems in the Ka-band (26.5GHz - 40GHz) allowing e.g.: video broadcasting, voice over IP (VoIP), internet acces to remote areas, ... Both need significant linear power amplification due to the high attenuation typical for this part of the spectrum, however, satellite systems demand a saturated output power which is easily an order of magnitude larger (output powers in excess of 30dBm / 1W). Monolithic microwave integrated circuits (MMICs) employing III-V chip technologies, e.g.: gallium arsenide (GaAs), gallium nitride (GaN), have historically been the preferred choice to implement efficient mm-wave power amplifiers (PA) with a high saturated output power (>30dBm). To further increase the commercial viability of consumer products in this market segment a low manufacturing cost for the power amplifier, together with the possible integration of additional functions, is highly desirable. These features are the strongpoint of silicon based chip technologies like CMOS and SiGe BiCMOS. However, these technologies have a breakdown voltage typically below 2V for nodes capable of millimeter-wave applications while III-V transistors with equivalent frequency performance demonstrate breakdown voltages in excess of 8V. Because of this, output powers of CMOS and SiGe BiCMOS Ka-band power amplifiers rarely exceed 20dBm which poses the main hurdle for using these technologies in satellite communication (SATCOM). To overcome the limited output power of a single amplifying cell in a silicon technology, caused by the low breakdown voltage, multiple power amplifiers cells need to have their output power effectively combined on-chip. This requires the on-chip integration of high-Q passives within a relative small area to realize both the impedance transformation, to create the optimal load impedance for the different amplifier cells, and implement an efficient on-chip power combination network. Compared to III-V technologies this is again a challenge due to the use of a silicon substrate which introduces higher losses. Once a large enough on-chip output power is created, the issue of launching this signal to the outside world remains. Moreover, due to the limited efficiency of mm-wave PAs, the generated on-chip heat will increase when larger output power are required. This means a chipto-board interface with a low thermal resistance and a low loss electrical connection needs to be devised. Proof of the viability of silicon as a serious candidate for the integration of medium and high power Ka-band amplifiers will only be delivered by long term research and the actual creation of such an amplifier. In this context, the initial goal for the presented work is proposed. This consists of the creation of a power amplifier with a saturated output power above 24dBm (preferably 27dBm), a gain larger than 20dB and an efficiency in excess of 10% (preferably 15%). These specifications where conceived with the precondition of using a 250nm SiGe BiCMOS technology (IHP’s SG25H3) with an fT of 110GHz and a collector to emitter breakdown voltage in open base conditions (BVCEO) of 2.3V. The use of this technology is a significant challenge due to the limited speed, rule of thumb is to have at least one fifth of the fT as the operating frequency, which reflects in the attainable power added efficiency (PAE). On the other hand, proving the possible implementation in this “older” technology shows great potential towards the future integration in a fast technology (e.g.: IHP’s SG13G2, ft =300GHz). Next to issues caused by limitations of the chip technology, the proposed specifications allows to identify generic difficulties with high power silicon PA design, e.g.: design of efficient on-chip power combiners, thermal management, single-ended to differential conversion, ... As this work is of an academic nature the intention of this design was to leave the beaten track and explore alternative topologies. This has led to the adoption of a driver stage using translinear loops for biasing and a transformer-type Wilkinson power combiner previously only used in cable television (CATV) applications. Although the power combiner showed 2dB more loss than expected due to higher than expected substrate losses, both topologies show promise for further integration. Furthermore, an in-depth analysis was performed on the output stage which uses positive feedback to increase its gain. The entire design consists of a four-way power combining class AB power amplifier together with test structures of which the performance was verified by means of probing. Due to the previously mentioned higher than expected loss in the on-chip power combiner, the total output power and power added efficiency (PAE) was 2dB lower than expected from simulations. The result is a saturated output power at 32GHz of 24.1dBm with a PAE of 7.2% and a small signal gain of 25dB. This demonstrates the capability of SiGe BiCMOS to implement PA’s for medium-power mm-wave applications. Moreover, to the best of the author’s knowledge, this PA achieves the second highest saturated output power when comparing SiGe BiCMOS PA’s with center frequency in or close to the Ka-band. The 1dB compression point of this amplifier lies at 22.7dBm which is close to saturated output power and results in a low spectral regrowth when compared to commercial GaAs PA’s (compared with 2MBaud 16QAM input signal at 10dB back-off). Many possible improvements to this design remain. The most important would be the re-design of the on-chip power combiner, possibly with a floating ground shield, to reduce the losses and increase the total output power and PAE. Also the porting of the design to a faster chip technology might result in a considerable increase of the output stage efficiency at the cost of needing to combine more amplifier cells. The transition to a faster chip technology would additionally allow to use this design for alternative mm-wave applications like automotive radar at 79GHz andWiGig at 60GHz