A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

1.25 Gbit/s ITU-T G.984.2 burst-mode transimpedance amplifier without reset pins

A

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization

This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C). The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔM topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology

Over the last two decade, digital signal processing (DSP) has grown rapidly in electronic systems to provide more reconfigureability and programmability in the applications, compared to analog component, which allows easier design and test automation. Digital circuit usage is increasing because of scaling properties of very large scale integration (VLSI) processes. This has allowed new generation of digital circuit to attain higher speed, more functionality per chip, low power dissipation, lower cost. Analog world, analog to digital converter (ADC) are used to convert the signal from analog to digital domain. For interfacing with DSP sample and hold (S/H) circuit is a key building block in, and is often used in front end of the ADCs to relax their timing requirement. The function of S/H circuit is to take samples to its input signal and hold these samples in its output for some period of time. The analog circuits in low voltage and low power have assumed great significance due to mixed-mode design required for modern electronic gadgets that demand portability and little power consumption. The mixed mode circuit has existence of both analog and digital circuits on the same chip and it is possible to have low voltage digital circuit in modern scaled-down technologies. However the same is not always true with analog circuits due to the constrains of device noise level and threshold voltage (VT) of MOSFET. Thus for analog circuit to co-exist on the same substrate along with digital system and share same supply voltage, the operation of analog circuit in low voltage environment is essential. The objective of this research is to design a low-voltage, high-performance S/H circuit that will address the above problems. A typical switch capacitor S/H circuit needs amplifier, switches and capacitor. New amplifier have been designed by using the architecture of single stage fully differential folded cascode low voltage operation transconductance amplifier (OTA) which has high gain and speed; the gin boosting technique was used for purpose of increasing the gain of the OTA. This technique does not affect the speed of the single stage. The transmission gate switches using CMOS devices, which have higher linearity and higher speed over a single MOS switch, have been designed for use in the S/H circuit. The switches are operated by clock generator with two non overlapping clock signals having low rise and fall time offering low noise for the S/H circuit. The clock was designed with 77.17ps rise and fall time to reduce the errors of driving MOS switches which results in higher linearity. The S/H circuit was designed to operate with 1.8V supply voltage in 0.18um technology. The sampling rate is 40MSPS with spurious free dynamic range (SFDR) 65.7dB and SNR 70dB

Assessment of ecosystem integrity of lowland dipterocarp forest ecosystem using remote sensing

Ecosystem Integrity Index (EII) is a concept to determine the quality or the health of an ecosystem. The EII development can assist forest managers and decision makers in the conservation effort and forest management in Malaysia through the development of a simple and easy-to-adopt index. The aim of this study is to assess and evaluate the EII through the development of forest structure empirical models from remotely sensed data for lowland dipterocarp forest in Malaysia. The objectives of this study are: (i) to assess the structure and composition of lowland dipterocarp forest in Malaysia, (ii) to develop empirical model for estimating stand structure from remotely sensed data, and (iii) to derive the ecosystem integrity index for lowland dipterocarp forest. Tree Basal Area (BA), aboveground biomass (AGB) and volume plot from plot data were used as dependent variables, while remote sensing data from Landsat, Pleiades and LiDAR were used as independent variables for model development. Tree plot census was carried out from 17 to 19 May 2016, while remote sensing data acquisition dates for Landsat, Pleiades and LiDAR were 13 March 2016, 24 January 2015 and April 2015 respectively. Forest Structure Modeling was carried out by means of a correlation analysis with the calibration of dependent and independent data to select the most significant and accurate remote sensing variables to derive empiric equation (model), fitting stage to select the best model with the highest coefficient of determination (R2) and the lowest root mean square error ( RMSE) validation of the final selected. The Ecosystem Integrity Index was developed by the average percentage of the predicted BA, AGB and model volume. The EII was categorised at five integrity levels as high (81–100%), medium high (61–80%), moderate (41–60%), medium low (21–40%) and low (0–20%). A total of 1035 trees with diameter at breast height (DBH) of 5.0 cm and above were recorded in 69.115 ha sampling areas. The total trees recorded represented 150 species from 87 genera and 34 families. Shorea macroptera (Dipterocarpaceae), S. leprosula (Dipterocarpaceae) and S. parviflora (Dipterocarpaceae) are three dominant species, with Species Important Value Index (SIVi) of 6.49%, 6.23% and 5.51%, respectively. Dipterocarpaceae is the most dominant with Family Important Value Index (FIVi) of 33.54%. The developed final model is robust and consistent with high R2 with range of 0.84 to 0.87. The final models constructed for AGB, BA and volume value of R2 are 0.85, 0.84 and 0.87 respectively. The RMSE of AGB, BA and volume model are 53.1 Mg/ha, 3.54 m2/ha and 46.4 m3/ha, respectively. The overall stand AGB, BA and volume for Sungai Menyala Forest Reserve is 282.29 Mg/ha, 17.68 m2/ha and 239.51 m3/ha. An Ecosystem Integrity Index (EII) assessment has been successfully demonstrated by this study with production of practical, multi-scaled, flexible, adjustable and policy-relevant index. The overall EII of Sungai Menyala Forest Reserve is in Category 3, which shows that the area is within the medium value