Land vehicle antennas for satellite mobile communications

The RF performance, size, pointing system, and cost were investigated concepts are: for a mechanically steered 1 x 4 tilted microstrip array, a mechanically steered fixed-beam conformal array, and an electronically steered conformal phased array. Emphasis is on the RF performance of the tilted 1 x 4 antenna array and methods for pointing the various antennas studied to a geosynchronous satellite. An updated version of satellite isolations in a two-satellite system is presented. Cost estimates for the antennas in quantities of 10,000 and 100,000 unites are summarized

Description and performance of a digital mobile satellite terminal

A major goal of the Mobile Satellite Experiment (MSAT-X) program at the Jet Propulsion Lab (JPL) is the development of an advanced digital terminal for use in land mobile satellite communication. The terminal has been developed to minimize the risk of applying advanced technologies to future commercial mobile satellite systems (MSS). Testing with existing L band satellites was performed in fixed, land mobile and aeronautical mobile environments. JPL's development and tests of its mobile terminal have demonstrated the viability of narrowband digital voice communications in a land mobile environment through geostationary satellites. This paper provides a consolidated description of the terminal architecture and the performance of its individual elements

A high stability semiconductor laser system for a 88^{88}Sr-based optical lattice clock

We describe a frequency stabilized diode laser at 698 nm used for high resolution spectroscopy of the 1S0-3P0 strontium clock transition. For the laser stabilization we use state-of-the-art symmetrically suspended optical cavities optimized for very low thermal noise at room temperature. Two-stage frequency stabilization to high finesse optical cavities results in measured laser frequency noise about a factor of three above the cavity thermal noise between 2 Hz and 11 Hz. With this system, we demonstrate high resolution remote spectroscopy on the 88Sr clock transition by transferring the laser output over a phase-noise-compensated 200 m-long fiber link between two separated laboratories. Our dedicated fiber link ensures a transfer of the optical carrier with frequency stability of 7 \cdot 10^{-18} after 100 s integration time, which could enable the observation of the strontium clock transition with an atomic Q of 10^{14}. Furthermore, with an eye towards the development of transportable optical clocks, we investigate how the complete laser system (laser+optics+cavity) can be influenced by environmental disturbances in terms of both short- and long-term frequency stability.Comment: 9 pages, 9 figures, submitted to Appl. Phys.

An Efficient Beam Steerable Antenna Array Concept for Airborne Applications

Deployment of a satellite borne, steerable antenna array with higher directivity and gain in Low Earth Orbit makes sense to reduce ground station complexity and cost, while still maintaining a reasonable link budget. The implementation comprises a digitally beam steerable phased array antenna integrated with a complete system, comprising the antenna, hosting platform, ground station, and aircraft based satellite emulator to facilitate convenient aircraft based testing of the antenna array and ground-space communication link. This paper describes the design, development and initial successful interim testing of the various subsystems. A two element prototype used in this increases the signal-to-noise ratio (SNR) by 3 dB which is corresponding to more than 10 times better bit error rate (BER)

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Special studies of AROD systems, concepts and designs Final report

Design and evaluation of development model for airborne range and orbit determination syste

A 10Gb/s data-dependent jitter equalizer

An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB

Experimental L-band SST satellite communications/surveillance terminal study. Volume 1 - Study summary

Study of design for experimental L band supersonic transport communications/surveillance termina

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m