Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Design of Power Efficient and High Slew Rate Class AB OPAMP

The paper deals with aim to design an OPAMP of Class AB to achieve high power efficiency and slew rate. To have high slew rate the focus of the proposed work as high slew rate contributes to the fast and dynamic output response. Power efficiency is driving factor from MOORE’S law. A Push pull OPAMP with current replicating branch is used to achieve symmetrical wave with high slew rate. Adaptive biasing is another technique employed to increase the slew rate. According to the Moore’s law, increase in power takes place in adaptive biasing due to increase in transistors, but the proposed circuit is best tradeoff between slew rate and power efficient factors. The existing work could only increase the slew rate by 4 to 5 times, but our proposed work increases it even further compared to the existing work, at the same time it results in decrease of power. In this work we are combining two techniques, namely adaptive biasing and current replicating branch which combine to result in better slew rate without increase in power. The proposed work is implemented with Cadence Virtuoso tool

Design of two-stage class AB CMOS buffers: a systematic approach

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW)

Pseudo-three-stage Miller op-amp with enhanced small-signal and large-signal performance

A simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V·pF/μs·μW large-signal figure of merit (FOM) and 17 MHz · pF/μW small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V · pF/μs · μW large-signal FOM and 92 MHz · pF/μW small-signal FOM with 0.5-V supply voltage.This work was supported by Grant TEC2016-80396- C2-R (AEI/FEDER)

Rail-to-Rail Operational in Low-Power Reconfigurable Analog Circuitry

Analog signal processing (ASP) can be used to decrease energy consumption by several orders of magnitude over completely digital applications. Low-power field programmable analog arrays (FPAA) have been previously used by analog designers to decrease energy consumption. Combining ASP with an FPAA, energy consumption of these systems can be further reduced. For ASP to be most functional, it must achieve rail-to-rail operation to maintain a high dynamic range. This work strives to further reduce power consumption in reconfigurable analog circuitry by presenting a novel data converter that utilizes ASP and rail-to-rail operation. Rail-to-Rail operation is achieved in the data converter with the use of an operational amplifier presented in this work. This efficient yet elementary data converter has been fabricated in a 0.5$\mu$m standard CMOS process. Additionally, this work looks deeper into the challenges of students working remotely, how MATLAB can be used to create circuit design tools, and how these developmental tools can be used by circuit design students