Planar surface-micromachined pressure sensor with a sub-surface, embedded reference pressure cavity

Planar, surface micromachined pressure sensors have been fabricated by an extension of the chemical-mechanical polishing (CMP) process. CMP eliminates many of the fabrication problems associated with the photolithography, dry etch, and metallization of non-planar devices. Furthermore, CMP adds additional design flexibility. The sensors are based upon deformable, silicon nitride diaphragms with polysilicon piezoresistors. Absolute pressure is detected by virtue of reference pressure cavities underneath the diaphragms. Process details are discussed and characteristics from many devices are presented

Planarization techniques for MEMS: enabling new structures and enhancing manufacturability

Planarization techniques such as chemical-mechanical polishing (CMP) have emerged as enabling technologies for the manufacturing of multi- level metal interconnects used in high-density Integrated Circuits (IC). An overview of general planarization techniques for MicroElectroMechanical Systems (MEMS) and, in particular, the extension of CMP from sub-micron IC manufacturing to the fabrication of complex surface-micromachined MEMS will be presented. Planarization technique alleviates processing problems associated with fabrication of multi-level polysilicon structures, eliminates design constraints linked with non-planar topography, and provides an avenue for integrating different process technologies. The CMP process and present examples of the use of CMP in fabricating MEMS devices such as microengines, pressure sensors, and proof masses for accelerometers along with its use for monolithically integrating MEMS devices with microelectronics are presented

Three-Dimensional MOS Process Development

A novel MOS technology for three-dimensional integration of electronic circuits on silicon substrates was developed. Selective epitaxial growth and epitaxial lateral overgrowth of monocrystalline silicon over oxidized silicon were employed to create locally restricted silicon-on-insulator device islands. Thin gate oxides were discovered to deteriorate in ambients typically used for selective epitaxial growth. Conditions of general applicability to silicon epitaxy systems were determined under which this deterioration was greatly reduced. Selective epitaxial growth needed to be carried out at low temperatures. However, crystalline defects increase as deposition temperatures are decreased. An exact dependence between the residual moisture content in epitaxial growth ambients, deposition pressure, and deposition temperature was determined which is also generally applicable to silicon epitaxy systems. The dependences of growth rates and growth rate uniformity on loading, temperature, flow rates, gas composition, and masking oxide thickness were investigated for a pancake type epitaxy reactor. A conceptual model was discussed attempting to describe the effects peculiar to selective epitaxial growth. The newly developed processing steps were assembled to fabricate three dimensional silicon-on-insulator capacitors. These capacitors were electrically evaluated. Surface state densities were in the order of 1O11cm-2 eV-1 and therefore within the range of applicability for a practical CMOS process. Oxidized polysilicon gates were overgrown with silicon by epitaxial lateral overgrowth. The epitaxial silicon was planarized and source and drain regions were formed above the polysilicon gates in Silicon-on-insulator material. The modulation of the source-drain current by bias changes of the buried gate was demonstrated

High density circuit technology, part 2

A multilevel metal interconnection system for very large scale integration (VLSI) systems utilizing polyimides as the interlayer dielectric material is described. A complete characterization of polyimide materials is given as well as experimental methods accomplished using a double level metal test pattern. A low temperature, double exposure polyimide patterning procedure is also presented

Post assembly process development for Monolithic OptoPill integration on silicon CMOS

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (leaves 108-110).Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis.by Yi-Shu Vivian Lei.S.M

Development of High-Speed Silicon Devices and Their Design with Advanced Physical Models

In the field of high-speed silicon devices, silicon bipolar junction transistors (BJTs) had played a major role from the 1970s to the end of the 1980s. However, in the 1990s complementary metal-oxide-semiconductor (CMOS) .field effect transistors (FETs) have been replacing their position. This dissertation explains the reasons why BJTs were suitable for high-speed operation. This is concluded from the development of technologies for BJTs and the analyses of devices fabricated with these technologies. At the same time it clarifies why they were replaced by CMOS transistors. The BJT's high driving capability and large power dissipation were the both sides of a sword. In the case of high-speed CMOS devices, the driving current of MOSFET should be large enough, and device design must be based on precise comprehension of carrier transport in MOSFETs. Therefore, we need accurate device model as well as rigid device-structure information obtained by experiments. This dissertation describes the device design methodology not only based on inverse modeling to extract device structures consistent with all kinds of experimental results but also based on simulations by generalized hydrodynamic model and full-band Monte Carlo model. The background and concept of the methodology is also discussed, and its necessity in future development is clarified. Moreover, hot carrier modeling is discussed by employing full-band Monte Carlo device simulation. Also, this dissertation clarifies the fact there is no experimental evidence for the difference between the surface and bulk impact ionization mechanism in silicon. The reported difference in the literature was only caused by an unsound application of the local field model and was just an artifact. Finally, by using these sophisticated models, the saturation drain current as well as hot carrier effects of subquarter micron MOSFETs are analyzed. MOSFET design strategy for the 0.1 μ　m regime is discussed and the importance of shallow junction for source/drain extension is also clarified.広島大学(Hiroshima University)博士(工学)doctora

Study of a New Silicon Epitaxy Technique: Confined Lateral Selective Epitaxial Growth

This work describes a significant new advance in the technique of silicon selective epitaxy called Confined Lateral Selective Epitaxial Growth (CLSEG). CLSEG is a method for forming thin films of single crystal silicon on top of an insulating layer or film. Such thin films are generically termed Silicon-On- Insulator (SOI), and1 allow dielectric isolation of integrated circuit elements, making them more efficient (faster with lower power), more resistant to radiation, and smaller than conventional integrated circuits, ionizing radiation than conventional integrated circuits. CLSEG offers advantages over current methods of achieving SOI by being easily manufactured, inherently reproducible, and having greater design flexibility. CLSEG is also adaptable to vertical stacking of devices in a circuit, in what is called three-dimensional integration, for even greater reductions in area. In addition, CLSEG can be used for a wide variety of sensor and micromachining application. This thesis describes the design and development of CLSEG, and compares it to the current state of the art in the fields of SOI and Selective Epitaxial Growth (SEG). CLSEG is accomplished by growing silicon selective epitaxy within a cavity; which is formed of dielectric materials upon a silicon substrate. The resulting SOI film can be made as thin as 0.1 micron, and tens of microns wide, with an unlimited length. In particular, there is now strong evidence that surface diffusivity of silicon adatoms on the dielectric masking layers is a significant contributor to the transport of silicon to the growth surface during SE G. CLSEG silicon material quality is evaluated by fabricating a variety of semiconductor devices in CLSEG films. These devices demonstrate the applicability of CLSEG to integrated circuits, and provide a basis of comparison between CLSEG-grown silicon and device-quality substrate silicon. Then, CLSEG is used to fabricate an advanced device structure, verifying the value and significance of this new epitaxy technique. In the final two chapters, CLSEG is evaluated as a technology, and compared to the current state of the art. Then, a method is presented Tor forming CLSEG with only one photolithography step, and a process is described for making a SOI film across an entire silicon wafer using CLSEG. These techniques may indicate the feasibility of using CLSEG for three dimensional integration of microelectronics. It is hoped that this work will establish a firm basis for further study of this interesting and valuable new technology

Manufacturing Design and Fabrication of 100 nm (Leff) CMOS Devices

A CMOS process for fabricating 100 nm CMOS devices has been developed. The Leff = 100 nm NMOS and PMOS transistors are the smallest ever that have been fabricated at RIT. The process is designed with Lpoly = 0.15 µm on 150 mm (6 ) Silicon wafers. The NMOS and PMOS transistors are designed to operate at 1.2 V supply voltage and exhibit 0.3 V threshold voltage. 30 Å silicon-dioxide gate dielectric with Nitrous Oxide (N2O), was found to be very thin for the first lot of 100 nm devices to operate. Individual process have been developed which include recessed oxide isolation, 30 Å gate oxide with N2O, polysilicon gate formation involving double exposure of polysilicon gate, nitride sidewall spacer formation, SALICIDE formation, precise contact cuts formation and metallization. All these individual processes have been developed and integrated into a 65 step CMOS process flow. Recipes have been developed for all process steps on variety of tools in the SMFL. The entire process has been updated on Manufacturing Execution System Application (MESA) as the ADV-CMOS 150 process which include instruction sets, specification ID\u27s, parameter groups, and document groups making it feasible for the same process to replicated in the future. Lots are fabricated and imperfections in the process are identified and fixed. Electrical sheet resistance results are compared to simulation results