Nanoparticle Engineering for Chemical-Mechanical Planarization

Increasing reliance on electronic devices demands products with high performance and efficiency. Such devices can be realized through the advent of nanoparticle technology. This book explains the physicochemical properties of nanoparticles according to each step in the chemical mechanical planarization (CMP) process, including dielectric CMP, shallow trend isolation CMP, metal CMP, poly isolation CMP, and noble metal CMP. The authors provide a detailed guide to nanoparticle engineering of novel CMP slurry for next-generation nanoscale devices below the 60nm design rule. This comprehensive text also presents design techniques using polymeric additives to improve CMP performance

세륨 산화물과 실리콘 기반의 웨이퍼의 상호작용에 대한 직접적, 정량적 분석 및 pH-범용적 CMP 후 세정 용액의 개발

학위논문(박사) -- 서울대학교대학원 : 공과대학 화학생물공학부, 2022. 8. 김재정.The size of the semiconductor devices reduces and their density increases, the semiconductor manufacturing process is becoming more important. In particular, the chemical mechanical polishing (CMP) process for silicon-based wafers mainly used in the shallow trench isolation (STI) process is increasing. CMP is a process of polishing the wafers at a relatively high pressure and speed, and a lot of contamination and scratches due to abrasives in the slurry are inevitably left. However, as the scaling down of semiconductor devices intensifies and the requirements in the manufacturing process increase, it is becoming more important to minimize contamination and scratches. Especially, the residual abrasives after STI-CMP may interfere with the uniform deposition of photoresist in lithography. Ceria abrasive is known to show high polishing rate on silicon oxide due to strong chemical interaction in contrast to silicon nitride, so nitride is usually used as a stopping layer. In the CMP process, the chemical interaction of ceria and silicon oxide is advantageous, but in the subsequent cleaning process to remove it, the chemical interaction becomes a troublesome. Therefore, it is very important to understand how the chemical interaction between the two occurs during the CMP and cleaning processes. In the past, cleaning was carried out using the lift-off method to etch the surface of silicon oxide using cleaning solutions such as standard cleaning 1 (SC-1), Sulfuric acid peroxide mixture (SPM), and diluted HF, but recently, new cleaning solution removing as little as possible the thinly deposited silicon oxide and selectively removing only ceria is necessary. In this study, the interaction of ceria abrasives on silicon nitride and oxide, was directly investigated through atomic force microscope (AFM). The adhesion energy was measured and compared to elucidate the reason why ceria could remove silicon oxide well compared to nitride. In addition, the change in adhesion energy value according to the surface oxidation state of ceria abrasive was measured by AFM, and the adsorption rate was measured by quartz crystal microbalance (QCM). Activation energy was calculated and compared using the measured adsorption rates at various temperature. To develop a cleaning solution that can be used at acidic pH, we developed a cleaning solution that can maintain the zeta potential negatively even under various conditions, and confirmed the cleaning efficiency.반도체 소자의 크기가 감소하고 밀도가 증가하면서 반도체 제조 공정의 중요성이 높아지고 있다. 특히 반도체 제조 공정 중 트랜지스터를 독립적으로 사용하기 위해 도입된 STI 공정에서 주로 사용되는 실리콘 기반의 웨이퍼들에 대한 화학적, 기계적 연마 공정의 중요도가 높아지고 있다. 화학적, 기계적 연마 공정은 비교적 강한 압력, 속도로 웨이퍼를 갈아내는 공정으로, 슬러리 내 연마재들로 인한 많은 오염 및 스크래치가 필연적으로 남게 된다. 그러나 반도체 공정의 필요조건이 높아지면서, 오염 및 스크래치를 최소한으로 줄이는 것이 매우 중요해지고 있다. 특히 STI 과정에서의 화학적, 기계적 연마 후 잔존 연마재는 이후 공정인 리소그래피 등에서 포토레지스트의 도포를 방해하고 단차를 유도하여 최종적으로 트랜지스터의 전기적 구동을 방해할 수 있다. STI 과정에서의 화학적, 기계적 연마에는 실리콘 산화물을 갈아내기 위해서 실리콘 산화물에 대한 선택도가 높은 세리아 연마재를 주로 사용한다. 세리아 연마재는 실리콘 산화물과 강한 화학적 상호작용을 하여 높은 연마율을 보이는 것으로 알려져 있으며, 실리콘 질화물은 잘 갈아내지 못하여, 질화물을 연마 제어 층으로 사용한다. 화학적, 기계적 연마 과정에서는 세리아와 실리콘 산화물 사이의 화학적 상호작용이 장점으로 작용하지만, 이후 이를 제거하는 세정 공정에서는 화학적 상호작용이 되려 골칫거리가 된다. 따라서 연마 과정 및 세정 과정에서 어떠한 메커니즘으로 둘의 화학적 상호작용이 일어나는지 이해하는 것이 매우 중요하다. 그리고 기존에는 기판 세정을 위해 일부 실리콘 산화막을 녹여내는 강한 세정 용액을 활용하여 실리콘 산화막 표면을 얇게 깎아내는 lift-off 방법으로 세정을 진행하였으나, 최근에는 얇게 도포된 실리콘 산화물을 최대한 적게 제거하며 세리아 연마재만 선택적으로 제거할 수 있는 세정 용액의 개발이 필요한 상황이다. 본 연구에서는 실리콘 질화물과 산화물 웨이퍼와 세리아 연마재 사이의 상호작용을 원자 힘 현미경을 통해 직접적으로 관찰하고, 접착 에너지를 측정하고 비교하여 실리콘 질화물에 비해 실리콘 산화물에서 세리아 연마재에 대한 세정이 더 어려운 이유를 밝히고자 하였다. 그리고 세리아 연마재의 표면 산화 상태에 따른 접착 에너지 값의 변화를 원자 힘 현미경을 통해 측정하였고, 수정 미세저울을 통해 흡착 속도를 측정하였다. 측정된 흡착 속도를 이용하여 활성화 에너지를 계산하고 비교하였다. 세리아와 실리콘 산화물 사이의 상호작용이 비교적 적은 산성 조건에서도 세리아 입자의 제타 전위가 음의 값을 유지할 수 있는 세정 용액의 개발을 위해 인산 기반의 첨가제들이 연구되었고, 세정 효율이 평가되었다.Chapter I. Introduction 1 1.1. Necessity of CMP in shallow trench isolation 1 1.2. Ceria abrasive for STI-CMP and its interaction with silicon oxide 6 1.3. Post-CMP cleaning process 10 1.4. Methods for analyzing the adsorption behavior 14 1.5. Main issues in post-CMP ceria cleaning and the necessity of pH-independent cleaning solution 19 1.6. Purpose of this research 26 Chapter II. Experimental 28 2.1. Interaction between ceria and silicon-based wafers 28 2.2. The impact of surficial oxidation state of ceria on the ceria-SiO2 interaction 31 2.3. Development of pH-independent post-CMP cleaning solution 34 Chapter III. Results and Discussion 38 3.1. Interaction between ceria and silicon-based wafers 38 3.1.1. Electrostatic interaction between ceria and Si3N4 or SiO2 38 3.1.2. Adhesion energy measurement with AFM 45 3.2. The impact of oxidation state of ceria on the ceria-SiO2 interaction 50 3.2.1. Chemical treatment for controlling oxidation state of ceria 50 3.2.2. Adhesion energy between ceria and SiO2 measured by AFM 58 3.2.3. Adsorption behavior of ceria on SiO2 investigated by QCM 62 3.3. Development of pH-independent post-CMP cleaning solution 68 3.3.1. Zeta potential of ceria nanoparticles with PA, EA, and ATMP 68 3.3.2. Cleaning solution for ceria abrasives 79 Chapter IV. Conclusion 83 References 86 국문 초록 93박

トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.北九州市立大

Modeling of chemical mechanical polishing for shallow trench isolation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 195-201).This thesis presents the nonlinear analysis, design, fabrication, and testing of an axial-gap magnetic induction micro machine, which is a two-phase planar motor in which the rotor is suspended above the stator via mechanical springs, or tethers. The micro motor is fabricated from thick layers of electroplated NiFe and copper, by our collaborators at Georgia Institute of Technology. The rotor and the stator cores are 4 mm in diameter each, and the entire motor is about 2 mm thick. During fabrication, SU-8 epoxy is used as a structural mold material for the electroplated cores. The tethers are designed to be compliant in the azimuthal direction, while preventing axial deflections and maintaining a constant air gap. This enables accurate measurements of deflections within the rotor plane via a computer microvision system. The small scale of the magnetic induction micro machine, in conjunction with the good thermal contact between its electroplated stator layers, ensures an isothermal device which can be cooled very effectively. Current densities over 109 A/m2 simultaneously through each phase is repeatedly achieved during experiments; this density is over two orders of magnitude larger than what can be achieved in conventional macro-scale machines.(cont.) More than 5 Nm of torque is obtained for an air gap of about 5 zm, making this micro motor the highest torque density micro-scale magnetic machine to date. About 0.3 buNm for the large air gap of 70 m is also achieved in systematic tests that reveal the influence of strong eddy-currents and associated nonlinear saturation within the micro motor Eddy-current effects are modeled using a finite-difference vector potential formulation. Its results demonstrate the presence of flux crowding on the stator surface, which leads to heavy saturation. To capture saturation effects, a fully nonlinear finite-difference time-domain simulation is developed to solve Maxwell's Equations within the computational space of the micro machine. To mitigate the inherent stiffness in the partial differential equations, the speed of light is artificially reduced by five orders of magnitude, taking special care that assumptions of magnetoquasistatic behavior are still met. The results from this model are in very good agreement with experimental data from the tethered magnetic induction micro motor.by Brian Lee.Ph.D

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Modeling and Optimization of Chemical Mechanical Planarization (Cmp) Using Neural Networks, Anfis and Evolutionary Algorithms

Higher density nano-devices and more metallization layers in microelectronic chips are unceasing goals to the present semiconductor industry. However, topological imperfections (higher non-uniformity) on the wafer surfaces and lower material removal rates (MRR) seriously hamper these pursuing motivations. Since'90, industry has been using chemical mechanical planarization/polishing (CMP) to overcome these obstacles for fabricating integrated circuits (IC) with interconnect geometries of < 0.18 &amp;#956;m. Obviously, the much needed understanding of this new technique is derived basically on the ancient lapping process. Modeling and simulation are critical to transfer CMP from an engineering 'art' to an engineering 'science'. Many efforts in CMP modeling have been made in the last decade, but the available analytical MRR and surface uniformity models cannot precisely describe this highly complicated process, involving simultaneous chemical reactions (and etching), and mechanical abrasion. In this investigation, neural networks (NN), adaptive-based-network fuzzy inference system (ANFIS), and evolutionary algorithms (EA) techniques were applied to successfully overcome the aforementioned modeling and simulation problems. In addition, fine-tuning techniques for re-modifying ANFIS models for sparse-data case using are developed. Furthermore, multi-objective evolutionary algorithms (MOEA) are firstly applied to search for the optimal input settings for CMP process to trade-off the higher MRR and lower non-Uniformity by using the previously constructed models. The results also show the simulation of MOEA optimization can certainly provide accurate guidance to search the optimal input settings for CMP process to produce lower non-uniform wafer surfaces under higher MRR.Mechanical & Aerospace Engineerin

Electrical Design for Manufacturability Solutions: Fast Systematic Variation Analysis and Design Enhancement Techniques

The primary objectives in this research are to develop computer-aided design (CAD) tools for Design for Manufacturability (DFM) solutions that enable designers to conduct more rapid and more accurate systematic variation analysis, with different design enhancement techniques. Four main CAD tools are developed throughout my thesis. The first CAD tool facilitates a quantitative study of the impact of systematic variations for different circuits' electrical and geometrical behavior. This is accomplished by automatically performing an extensive analysis of different process variations (lithography and stress) and their dependency on the design context. Such a tool helps to explore and evaluate the systematic variation impact on any type of design. Secondly, solutions in the industry focus on the "design and then fix philosophy", or "fix during design philosophy", whereas the next CAD tool involves the "fix before design philosophy". Here, the standard cell library is characterized in different design contexts, different resolution enhancement techniques, and different process conditions, generating a fully DFM-aware standard cell library using a newly developed methodology that dramatically reduce the required number of silicon simulations. Several experiments are conducted on 65nm and 45nm designs, and demonstrate more robust and manufacturable designs that can be implemented by using the DFM-aware standard cell library. Thirdly, a novel electrical-aware hotspot detection solution is developed by using a device parameter-based matching technique since the state-of-the-art hotspot detection solutions are all geometrical based. This CAD tool proposes a new philosophy by detecting yield limiters, also known as hotspots, through the model parameters of the device, presented in the SPICE netlist. This novel hotspot detection methodology is tested and delivers extraordinary fast and accurate results. Finally, the existing DFM solutions, mainly address the digital designs. Process variations play an increasingly important role in the success of analog circuits. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. The fourth CAD solution, proposed in this thesis, introduces a variability-aware DFM solution that detects, analyze, and automatically correct hotspots for analog circuits

5nm 이하 3D Transistors의 Self-Heating 및 전열특성분석 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·컴퓨터공학부, 2021.8. 신형철.In this thesis, Self-Heating Effect (SHE) is investigated using TCAD simulations in various Sub-10-nm node Field Effect Transistor (FET). As the node decreases, logic devices have evolved into 3D MOSFET structures from Fin-FET to Nanosheet-FET. In the case of 3D MOSFET, there are thermal reliability issues due to the following reasons: ⅰ) The power density of the channel is high, ⅱ) The channel structure surrounded by SiO2, ⅲ) The overall low thermal conductivity characteristics due to scaling down. Many papers introduce the analysis and prediction of temperature rise by SHE in the device, but there are no papers presenting the content of mitigation of temperature rise. Therefore, we have studied the methods of decreasing the maximum lattice temperature (TL,max) such as shallow trench isolation (STI) composition engineering in Fin-FET, thermal analysis according to DC/AC/duty cycle in nanowire-FET, and active region ( e.g., gate metal thickness, channel width, channel number etc..) optimization in nanosheet-FET. In addition, lifetime affected by hot carrier injection (HCI) / bias-temperature instability (BTI) is also analyzed according to various thermal relaxation methods presented.이 논문에서는 다양한 Sub-10nm 노드 전계 효과 트랜지스터 (FET)에서 TCAD 시뮬레이션을 사용하여 자체 발열 효과 (SHE)를 조사합니다. 노드가 감소함에 따라 논리 장치는 Fin-FET에서 Nanosheet-FET로 3D MOSFET 구조로 진화했습니다. 3D MOSFET의 경우 ⅰ) 채널의 전력 밀도가 높음, ⅱ) SiO2로 둘러싸인 채널 구조, ⅲ) 축소로 인해 전체적으로 낮은 열전도 특성 등 다음과 같은 이유로 열 신뢰성 문제가 있습니다. 한편, 많은 논문이 device에서 SHE에 의한 온도 상승의 분석 및 예측을 소개하지만 온도 상승 완화의 내용을 제시하는 논문은 거의 없습니다. 따라서 Fin-FET의 STI (Shallow Trench Isolation) 구성 공학, nanowire-FET의 DC / AC / 듀티 사이클에 따른 열 분석, nanosheet-FET에서 소자의 중요영역(예: 게이트 금속 두께, 채널 폭, 채널 번호 등)의 최적화를 통해서 최대 격자 온도 (TL,max)를 낮추는 방법등을 연구했습니다. 또한 더 나아가서 HCI (Hot Carrier Injection) / BTI (Bias-Temperature Instability)의 영향을 받는 수명도 제시된 다양한 열 완화 방법에 따라 분석하여 소자의 제작에 있어 열적 특성과 수명을 좋게 만드는 지표를 제시합니다 .Chapter 1 Introduction 1 1.1. Development of Semconductor structure 1 1.2. Self-Heating Effect issues in semiconductor devices 3 Chapter 2 Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing Ioff in Various Sub-10-nm 3-D Transistor 7 2.1. Introduction 7 2.2. Device Structure and Simulation Condition 7 2.3. Results and Discussion 12 2.4. Summary 27 Chapter 3 Analysis of Self Heating Effect in DC/AC Mode in Multi-channel GAA-Field Effect Transistor 32 3.1. Introduction 32 3.2. Multi-Channel Nanowire FET and Back End Of Line 33 3.3. Work Flow and Calibration Process 35 3.4. More Detailed Thermal Simulation of Nanowire-FET 37 3.5. Performance Analysis by Number of Channels 38 3.6. DC Characteristic of SHE in Nanowire-FETs 40 3.7. AC Characteristics of SHE in Nanowire-FETs 43 3.8. Summary 51 Chapter 4 Self-Heating and Electrothermal Properties of Advanced Sub-5-nm node Nanoplate FET 56 4.1. Introduction 56 4.2. Device Structure and Simulation Condition 57 4.3. Thermal characteristics by channel number and width 62 4.4. Thermal characteristics by inter layer-metal thickness (TM) 64 4.5. Life Time Prediction 65 4.6. Summary 67 Chapter 5 Study on Self Heating Effect and life time in Vertical-channel Field Effect Transistor 72 5.1. Introduction 72 5.2. Device Structure and Simulation Condition 72 5.3. Temperature and RTH according to channel width(TW) 76 5.4. Thermal properties according to air spacers and air gap 77 5.5. Ion boosting according to Channel numbers 81 5.6. Temperature imbalance of multi-channel VFETs 82 5.7. Mitigation of the channel temperature imbalance 86 5.8. Life time depending on various analysis conditions 88 5.9. Summary 89 Chapter 6 Conclusions 93 Appendix A. A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models 95 A.1. Introduction 95 A.2. Overall Schematic of the RF MOSFET Model 97 A.3. Verification of the DC Characteristics of the RF MOSFET Model 98 A.4. Verification of the MOSFET Model with Measured Y-parameters 100 A.5. Verification of the MOSFET Model with Measured Noise Parameters 101 A.6. Thermal Noise Extraction and Modeling (TNOIMOD = 0) 103 A.7. Verification of the Enhanced Model with Noise Parameters 112 A.8. Holistic Model (TNOIMOD = 1) 114 A.9. Evaluation the validity of the model for drain bias 115 A.10. Conclusion 117 Abstract in Korean 122박