Distributed video coding for wireless video sensor networks: a review of the state-of-the-art architectures

Distributed video coding (DVC) is a relatively new video coding architecture originated from two fundamental theorems namely, Slepian–Wolf and Wyner–Ziv. Recent research developments have made DVC attractive for applications in the emerging domain of wireless video sensor networks (WVSNs). This paper reviews the state-of-the-art DVC architectures with a focus on understanding their opportunities and gaps in addressing the operational requirements and application needs of WVSNs

Self-concatenated coding and multi-functional MIMO aided H.264 video telephony

Abstract— Robust video transmission using iteratively detected Self-Concatenated Coding (SCC), multi-dimensional Sphere Packing (SP) modulation and Layered Steered Space-Time Coding (LSSTC) is proposed for H.264 coded video transmission over correlated Rayleigh fading channels. The self-concatenated convolutional coding (SECCC) scheme is composed of a Recursive Systematic Convolutional (RSC) code and an interleaver, which is used to randomise the extrinsic information exchanged between the self-concatenated constituent RSC codes. Additionally, a puncturer is employed for improving the achievable bandwidth efficiency. The convergence behaviour of the MIMO transceiver advocated is investigated with the aid of Extrinsic Information Transfer (EXIT) charts. The proposed system exhibits an Eb /N0 gain of about 9 dB at the PSNR degradation point of 1 dB in comparison to the identical-rate benchmarker scheme

Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available High Definition (HD) video formats, the computational complexity of De full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, ill this paper, we present Dynamically Variable Step Search (DVSS) ME algorithm for Processing high definition video formats and a dynamically reconfigurable hardware efficiently implementing DVSS algorithm. The architecture for efficiently implementing DVSS algorithm. The simulation results showed that DVSS algorithm performs very close to FS algorithm by searching much fewer search locations than FS algorithm and it outperforms successful past search ME algorithms by searching more search locations than these algorithms. The proposed hardware is implemented in VHDL and is capable, of processing high definition video formats in real time. Therefore, it can be used in consumer electronics products for video compression, frame rate up-conversion and de-interlacing(1)

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

Iterative H.264 Source and Channel Decoding Using Sphere Packing Modulation Aided Layered Steered Space-Time Codes

The conventional two-stage turbo-detection schemes generally suffer from a Bit Error Rate (BER) floor. In this paper we circumvent this deficiency by proposing a three-stage turbo detected Sphere Packing (SP) modulation aided Layered Steered Space-Time Coding (LSSTC) scheme for H.264 coded video transmission over correlated Rayleigh fading channels. The soft-bit assisted H.264 coded bit-stream is protected using low-complexity short-block codes (SBCs), combined with a rate-1 recursive inner precoder is employed as an intermediate code which has an infinite impulse response and hence beneficially spreads the extrinsic information across the constituent decoders. This allows us to avoid having a BER floor. Additionally, the convergence behaviour of this serially concatenated scheme is investigated with the aid of Extrinsic Information Transfer (EXIT) Charts. The proposed system exhibits an Eb/N0 gain of about 12 dB in comparison to the benchmark scheme carrying out iterative source-channel decoding as well as Layered Steered Space-Time Coding (LSSTC) aided Sphere Packing (SP)demodulation, but dispensing with the optimised SBCs

Iterative source and channel decoding relying on correlation modelling for wireless video transmission

Since joint source-channel decoding (JSCD) is capable of exploiting the residual redundancy in the source signals for improving the attainable error resilience, it has attracted substantial attention. Motivated by the principle of exploiting the source redundancy at the receiver, in this treatise we study the application of iterative source channel decoding (ISCD) aided video communications, where the video signal is modelled by a first-order Markov process. Firstly, we derive reduced-complexity formulas for the first-order Markov modelling (FOMM) aided source decoding. Then we propose a bit-based iterative horizontal vertical scanline model (IHVSM) aided source decoding algorithm, where a horizontal and a vertical source decoder are employed for exchanging their extrinsic information using the iterative decoding philosophy. The iterative IHVSM aided decoder is then employed in a forward error correction (FEC) encoded uncompressed video transmission scenario, where the IHVSM and the FEC decoder exchange softbit-information for performing turbo-like ISCD for the sake of improving the reconstructed video quality. Finally, we benchmark the attainable system performance against a near-lossless H.264/AVC video communication system and the existing FOMM based softbit source decoding scheme, where The financial support of the RC-UK under the auspices of the India-UK Advanced Technology Centre (IU-ATC) and that of the EU under the CONCERTO project as well as that of the European Research Council’s Advanced Fellow Grant is gratefully acknowledged. The softbit decoding is performed by a one-dimensional Markov model aided decoder. Our simulation results show that Eb=N0 improvements in excess of 2.8 dB are attainable by the proposed technique in uncompressed video applications

Error-resilient performance of Dirac video codec over packet-erasure channel

Video transmission over the wireless or wired network requires error-resilient mechanism since compressed video bitstreams are sensitive to transmission errors because of the use of predictive coding and variable length coding. This paper investigates the performance of a simple and low complexity error-resilient coding scheme which combines source and channel coding to protect compressed bitstream of wavelet-based Dirac video codec in the packet-erasure channel. By partitioning the wavelet transform coefficients of the motion-compensated residual frame into groups and independently processing each group using arithmetic and Forward Error Correction (FEC) coding, Dirac could achieves the robustness to transmission errors by giving the video quality which is gracefully decreasing over a range of packet loss rates up to 30% when compared with conventional FEC only methods. Simulation results also show that the proposed scheme using multiple partitions can achieve up to 10 dB PSNR gain over its existing un-partitioned format. This paper also investigates the error-resilient performance of the proposed scheme in comparison with H.264 over packet-erasure channel