7,277 research outputs found
A high-Tc 4-bit periodic threshold analog-to-digital converter
Using ramp-type Josephson junctions a 4-bit periodic threshold ADC has been designed, fabricated and tested. Practical design constraints will be discussed in terms of noise immunity, flux flow, available technology, switching speed etc. In a period of four years we fabricated about 100 chips in order to bring the technology to an acceptable level and to test various designs and circuit layouts. This resulted in a basic comparator that is rather insensitive to the stray field generated by the analog input signal or variations in mask alignment during fabrication. The input signal is fed into the comparators using a resistive divider network. Full functionality at low frequencies has been demonstrate
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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals
Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs
In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC
On Low-Resolution ADCs in Practical 5G Millimeter-Wave Massive MIMO Systems
Nowadays, millimeter-wave (mmWave) massive multiple-input multiple-output
(MIMO) systems is a favorable candidate for the fifth generation (5G) cellular
systems. However, a key challenge is the high power consumption imposed by its
numerous radio frequency (RF) chains, which may be mitigated by opting for
low-resolution analog-to-digital converters (ADCs), whilst tolerating a
moderate performance loss. In this article, we discuss several important issues
based on the most recent research on mmWave massive MIMO systems relying on
low-resolution ADCs. We discuss the key transceiver design challenges including
channel estimation, signal detector, channel information feedback and transmit
precoding. Furthermore, we introduce a mixed-ADC architecture as an alternative
technique of improving the overall system performance. Finally, the associated
challenges and potential implementations of the practical 5G mmWave massive
MIMO system {with ADC quantizers} are discussed.Comment: to appear in IEEE Communications Magazin
High-resolution wide-band Fast Fourier Transform spectrometers
We describe the performance of our latest generations of sensitive wide-band
high-resolution digital Fast Fourier Transform Spectrometer (FFTS). Their
design, optimized for a wide range of radio astronomical applications, is
presented. Developed for operation with the GREAT far infrared heterodyne
spectrometer on-board SOFIA, the eXtended bandwidth FFTS (XFFTS) offers a high
instantaneous bandwidth of 2.5 GHz with 88.5 kHz spectral resolution and has
been in routine operation during SOFIA's Basic Science since July 2011. We
discuss the advanced field programmable gate array (FPGA) signal processing
pipeline, with an optimized multi-tap polyphase filter bank algorithm that
provides a nearly loss-less time-to-frequency data conversion with
significantly reduced frequency scallop and fast sidelobe fall-off. Our digital
spectrometers have been proven to be extremely reliable and robust, even under
the harsh environmental conditions of an airborne observatory, with
Allan-variance stability times of several 1000 seconds. An enhancement of the
present 2.5 GHz XFFTS will duplicate the number of spectral channels (64k),
offering spectroscopy with even better resolution during Cycle 1 observations.Comment: Accepted for publication in A&A (SOFIA/GREAT special issue
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