가변기능형 아날로그 블록 기반의 현장 프로그램이 가능한 혼성 신호 집적회로의 설계

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 김재하.Fast-emerging electronic device applications demand a variety of new mixed-signal ICs to be developed in fast cycle and with low cost. While field-programmable gate arrays (FPGAs) are established solutions for timely and low-cost prototyping of digital systems, their counterpart for mixed-signal circuits is still an active area for research. This thesis presents a design of a field-programmable IC for analog/mixed-signal circuits, which solves many challenges with the previous works by performing analog functions in time domain. In order to realize the field-programmable analog functionality, time-domain configurable analog block (TCAB) is proposed. A single TCAB can be programmed to various analog circuits, including a time-to-digital converter, digitally-controlled oscillator, digitally-controlled delay cell, digital pulse-width modulator, and phase interpolator. In addition, the TCABs convey and process analog information using the frequency, pulse width, delay, or phase of digital pulses or pulse sequences, rather than using analog voltage or current signals for less susceptibility to attenuation and noise. This analog information expressed in the digital pulses makes it easy to implement scalable programmable interconnects among the TCABs. The architecture of field-programmable IC capable of emulating todays diverse mixed-signal systems is also introduced. In addition to the TCABs, the proposed IC also includes arrays of configurable logic blocks (CLBs) and programmable arithmetic logic units (ALUs) for programmable digital functions. By programming the functionality of the TCAB, CLB, and ALU arrays and configuring the interconnects, the chip can implement various mixed-signal systems. A prototype IC fabricated with 65-nm CMOS technology demonstrates the versatile programmability of the proposed TCAB and the IC by being successfully operated as a 1-GHz phase-locked loop with a 12.3-psrms integrated jitter, as a 50-MS/s analog-to-digital converter with a 32.5-dB SNDR, and as a 1.2-to-0.7V DC–DC converter with 95.5 % efficiency.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATIONS 1 1.2 THESIS CONTRIBUTION AND ORGANIZATION 5 CHAPTER 2 TIME-DOMAIN CONFIGURABLE ANALOG BLOCK 7 2.1 OVERVIEW OF THE TCAB 9 2.1.1. RECONFIGURABLE FUNCTIONALITY 9 2.1.2. TIME-DOMAIN SIGNAL PROCESSING 14 2.2 CIRCUIT IMPLEMENTATION OF THE TCAB 17 2.3 VERSATILE PROGRAMMABILITY OF TCAB 24 2.3.1. RELAXATION OSCILLATOR 24 2.3.2. DIGITALLY-CONTROLLED OSCILLATOR 28 2.3.3. DIGITAL PULSE-WIDTH MODULATOR 32 2.3.4. GATED OSCILLATOR 34 2.3.5. DIGITALLY-CONTROLLED DELAY CELL 35 2.3.6. PHASE INTERPOLATOR 37 2.3.7. MULTIPHASE DCO 39 2.3.8. NON-OVERLAPPING PULSE GENERATOR 41 2.4 TCAB ARRAY WITH PROGRAMMABLE INTERCONNECTS 43 2.4.1. TCAB ARRAY COMPOSITION 43 2.4.2. PROGRAMMABLE INTERCONNECTS 44 CHAPTER 3 PROPOSED ARCHITECTURE FOR FIELD-PROGRAMMABLE MIXED-SIGNAL IC 49 CHAPTER 4 CIRCUIT IMPLEMENTATION 54 4.1 CONFIGURABLE LOGIC BLOCK ARRAY 55 4.1.1. CONFIGURABLE LOGIC BLOCK 55 4.1.2. CLB ARRAY 56 4.2 ARITHMETIC LOGIC UNIT ARRAY 58 4.2.1. ARITHMETIC LOGIC UNIT 58 4.2.2. ALU ARRAY 61 4.3 INTERFACING BLOCKS 63 4.3.1. VOLTAGE-TO-TIME CONVERTER 64 4.3.2. PHASE-FREQUENCY DETECTOR 65 4.3.3. COUNTER BLOCK 66 4.3.4. TIME-TO-VOLTAGE CONVERTER 68 4.4 PROGRAM METHOD 70 CHAPTER 5 MIXED-SIGNAL EXAMPLES AND EXPERIMENTAL RESULTS 73 5.1 MEASUREMENT RESULTS OF TCAB 76 5.1.1. DIGITAL PULSE-WIDTH MODULATOR 76 5.1.2. DIGITALLY-CONTROLLED OSCILLATOR 79 5.1.3. GATED OSCILLATOR 81 5.2 DIGITAL PHASE-LOCKED LOOP 83 5.3 ANALOG-TO-DIGITAL CONVERTER 89 5.4 DCDC CONVERTER 94 CHAPTER 6 CONCLUSION 99 BIBLIOGRAPHY 101 초 록 108Docto

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Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

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The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA.

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

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Compressive Sensing (CS) is a signal processing technique which reduces the number of samples taken per frame to decrease energy, storage, and data transmission overheads, as well as reducing time taken for data acquisition in time-critical applications. The tradeoff in such an approach is increased complexity of signal reconstruction. While several algorithms have been developed for CS signal reconstruction, hardware implementation of these algorithms is still an area of active research. Prior work has sought to utilize parallelism available in reconstruction algorithms to minimize hardware overheads; however, such approaches are limited by the underlying limitations in CMOS technology. Herein, the MFPA (Mixed-signal Field Programmable Array) approach is presented as a hybrid spin-CMOS reconfigurable fabric specifically designed for implementation of CS data sampling and signal reconstruction. The resulting fabric consists of 1) slice-organized analog blocks providing amplifiers, transistors, capacitors, and Magnetic Tunnel Junctions (MTJs) which are configurable to achieving square/square root operations required for calculating vector norms, 2) digital functional blocks which feature 6-input clockless lookup tables for computation of matrix inverse, and 3) an MRAM-based nonvolatile crossbar array for carrying out low-energy matrix-vector multiplication operations. The various functional blocks are connected via a global interconnect and spin-based analog-to-digital converters. Simulation results demonstrate significant energy and area benefits compared to equivalent CMOS digital implementations for each of the functional blocks used: this includes an 80% reduction in energy and 97% reduction in transistor count for the nonvolatile crossbar array, 80% standby power reduction and 25% reduced area footprint for the clockless lookup tables, and roughly 97% reduction in transistor count for a multiplier built using components from the analog blocks. Moreover, the proposed fabric yields 77% energy reduction compared to CMOS when used to implement CS reconstruction, in addition to latency improvements

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D

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