Hibernus++: a self-calibrating and adaptive system for transiently-powered embedded devices

Energy harvesters are being used to power autonomous systems, but their output power is variable and intermittent. To sustain computation, these systems integrate batteries or supercapacitors to smooth out rapid changes in harvester output. Energy storage devices require time for charging and increase the size, mass and cost of systems. The field of transient computing moves away from this approach, by powering the system directly from the harvester output. To prevent an application from having to restart computation after a power outage, approaches such as Hibernus allow these systems to hibernate when supply failure is imminent. When the supply reaches the operating threshold, the last saved state is restored and the operation is continued from the point it was interrupted. This work proposes Hibernus++ to intelligently adapt the hibernate and restore thresholds in response to source dynamics and system load properties. Specifically, capabilities are built into the system to autonomously characterize the hardware platform and its performance during hibernation in order to set the hibernation threshold at a point which minimizes wasted energy and maximizes computation time. Similarly, the system auto-calibrates the restore threshold depending on the balance of energy supply and consumption in order to maximize computation time. Hibernus++ is validated both theoretically and experimentally on microcontroller hardware using both synthesized and real energy harvesters. Results show that Hibernus++ provides an average 16% reduction in energy consumption and an improvement of 17% in application execution time over stateof- the-art approaches

The Potential of Electrospinning to Enable the Realization of Energy-Autonomous Wearable Sensing Systems

The market for wearable electronic devices is experiencing significant growth and increasing potential for the future. Researchers worldwide are actively working to improve these devices, particularly in developing wearable electronics with balanced functionality and wearability for commercialization. Electrospinning, a technology that creates nano/microfiber-based membranes with high surface area, porosity, and favorable mechanical properties for human in vitro and in vivo applications using a broad range of materials, is proving to be a promising approach. Wearable electronic devices can use mechanical, thermal, evaporative and solar energy harvesting technologies to generate power for future energy needs, providing more options than traditional sources. This review offers a comprehensive analysis of how electrospinning technology can be used in energy-autonomous wearable wireless sensing systems. It provides an overview of the electrospinning technology, fundamental mechanisms, and applications in energy scavenging, human physiological signal sensing, energy storage, and antenna for data transmission. The review discusses combining wearable electronic technology and textile engineering to create superior wearable devices and increase future collaboration opportunities. Additionally, the challenges related to conducting appropriate testing for market-ready products using these devices are also discussed

A Novel Micro Piezoelectric Energy Harvesting System

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2007Bu tezde yeni bir titreşim temelli mikro enerji harmanlayıcı sistemi önerilmiştir. Titreşimler ve ani hareketler, mekanik yapının sadece eğilmesine değil aynı zamanda gerilmesine yol açar, bu sayede sistem doğrusal olmayan bölgede çalışır. İnce piezoelektrik film tabakası mekanik stresi elektrik enerjisine çevirir. Mikrowatt mertebesinde güç seviyeleri mm3’lük aletlerle elde edilebilir, bu da güneş panellerinde elde edilen güç yoğunlukları kadar yüksektir. Algılayıcı kabiliyeti sayesinde bilgi depolayabilen, kum tanesi büyüklüğünde olan ve üretiminde kullanılan temel malzeme silikon olan bu aletler “zeki kum” olarak isimlendirilmiştir. Mekanik yapının modellenmesi ve tasarımı geliştirilmiş ve üretim sonuçları da ayrıca verilmiştir. Sistemin bilgi gönderebilmesi ve alabilmesi amacıyla iyi bilinen RFID teknolojisi tabanlı bir kablosuz haberleşme yöntemi önerilmiştir. Bu bağlamda, paket taşımacılığında sürekli ivme denetleme, sınır güvenliği için kendinden beslemeli algılayıcılar, çabuk bozulan yiyeceklerin taşımacılığında sıcaklık denetleme ve pilsiz kalp atışı algılayıcı gibi birçok uygulama önerilmiştir.In this thesis, a novel, vibration based micro energy harvester system is proposed. Vibrations or sudden movements cause the mechanical structure does not only bend but also stretch, thus working in non-linear regime. The piezoelectric thin film layer converts the mechanical stress into the electrical energy. Microwatts of power can be achieved with a mm3 device which yields a high power density levels on the order of the solar panels. This device is named “smart sand”, because it has also sensor capabilities that can store information, its size is almost a sand grain and the main material used for the fabrication is silicon. The modeling and design of the mechanical structure has been developed and fabrication results have also been given in the thesis. In order for the system to send and receive the information, a wireless communication scheme is proposed which is based on the well-known RFID technology. In this concept, several applications are proposed such as continuous acceleration monitoring in package delivery, self-powered sensors for homeland security, temperature monitoring of the perishable food item delivery and a batteryless heart rate sensor.DoktoraPh

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumption and high energy efficiency have emerged as the two key criteria for embedded microprocessor design. In this thesis we present a range of microarchitectural low-power design techniques which enable the increase of performance for embedded microprocessors and/or the reduction of energy consumption, e.g., through voltage scaling. In the context of cryptographic applications, we explore the effectiveness of instruction set extensions (ISEs) for a range of different cryptographic hash functions (SHA-3 candidates) on a 16-bit microcontroller architecture (PIC24). Specifically, we demonstrate the effectiveness of light-weight ISEs based on lookup table integration and microcoded instructions using finite state machines for operand and address generation. On-node processing in autonomous wireless sensor node devices requires deeply embedded cores with extremely low power consumption. To address this need, we present TamaRISC, a custom-designed ISA with a corresponding ultra-low-power microarchitecture implementation. The TamaRISC architecture is employed in conjunction with an ISE and standard cell memories to design a sub-threshold capable processor system targeted at compressed sensing applications. We furthermore employ TamaRISC in a hybrid SIMD/MIMD multi-core architecture targeted at moderate to high processing requirements (> 1 MOPS). A range of different microarchitectural techniques for efficient memory organization are presented. Specifically, we introduce a configurable data memory mapping technique for private and shared access, as well as instruction broadcast together with synchronized code execution based on checkpointing. We then study an inherent suboptimality due to the worst-case design principle in synchronous circuits, and introduce the concept of dynamic timing margins. We show that dynamic timing margins exist in microprocessor circuits, and that these margins are to a large extent state-dependent and that they are correlated to the sequences of instruction types which are executed within the processor pipeline. To perform this analysis we propose a circuit/processor characterization flow and tool called dynamic timing analysis. Moreover, this flow is employed in order to devise a high-level instruction set simulation environment for impact-evaluation of timing errors on application performance. The presented approach improves the state of the art significantly in terms of simulation accuracy through the use of statistical fault injection. The dynamic timing margins in microprocessors are then systematically exploited for throughput improvements or energy reductions via our proposed instruction-based dynamic clock adjustment (DCA) technique. To this end, we introduce a 6-stage 32-bit microprocessor with cycle-by-cycle DCA. Besides a comprehensive design flow and simulation environment for evaluation of the DCA approach, we additionally present a silicon prototype of a DCA-enabled OpenRISC microarchitecture fabricated in 28 nm FD-SOI CMOS. The test chip includes a suitable clock generation unit which allows for cycle-by-cycle DCA over a wide range with fine granularity at frequencies exceeding 1 GHz. Measurement results of speedups and power reductions are provided

Online learning of physics during a pandemic: A report from an academic experience in Italy

The arrival of the Sars-Cov II has opened a new window on teaching physics in academia. Frontal lectures have left space for online teaching, teachers have been faced with a new way of spreading knowledge, adapting contents and modalities of their courses. Students have faced up with a new way of learning physics, which relies on free access to materials and their informatics knowledge. We decided to investigate how online didactics has influenced students’ assessments, motivation, and satisfaction in learning physics during the pandemic in 2020. The research has involved bachelor (n = 53) and master (n = 27) students of the Physics Department at the University of Cagliari (N = 80, 47 male; 33 female). The MANOVA supported significant mean differences about gender and university level with higher values for girls and master students in almost all variables investigated. The path analysis showed that student-student, student-teacher interaction, and the organization of the courses significantly influenced satisfaction and motivation in learning physics. The results of this study can be used to improve the standards of teaching in physics at the University of Cagliar