Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Wideband CMOS low noise amplifiers

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW1, using 1.2 V supply. The two LNA approaches proposed in this thesis are validated by simulation and by measurement results, and are included in a receiver front-end for biomedical applications (ISM and WMTS), as an example; however, they have a wider range of applications

Design of broadband inductor-less RF front-ends with high dynamic range for G.hn

System-on-Chip (SoC) was adopted in recent years as one of the solutions to reduce the cost of integrated systems. When the SoC solution started to be used, the final product was actually more expensive due to lower yield. The developments in integrated technology through the years allowed the integration of more components in lesser area with a better yield. Thus, SoCs became a widely used solution to reduced the cost of the final product, integrating into a single-chip the main parts of a system: analog, digital and memory. As integrated technology kept scaling down to allow a higher density of transistors and thus providing more functionality with the same die area, the analog RF parts of the SoC became a bottleneck to cost reduction as inductors occupy a large die area and do not scale down with technology. Hence, the trend moves toward the research and design of inductor-less SoCs that further reduce the cost of the final solution. Also, as the demand for home networking high-data-rates communication systems has increased over the last decade, several standards have been developed to satisfy the requirements of each application, the most popular being wireless local area networks (WLANs) based on the IEEE 802.11 standard. However, poor signal propagation across walls make WLANs unsuitable for high-speed applications such as high-definition in-home video streaming, leading to the development of wired technologies using the existing in-home infrastructure. The ITU-T G.hn recommendation (G.9960 and G.9961) unifies the most widely used wired infrastructures at home (coaxial cables, phone lines and power lines) into a single standard for high-speed data transmission of up to 1 Gb/s. The G.hn recommendation defines a unified networking over power lines, phone lines and coaxial cables with different plans for baseband and RF. The RF-coax bandplan, where this thesis is focused, uses 50 MHz and 100 MHz bandwidth channels with 256 and 512 carriers respectively. The center frequency can range from 350 MHz to 2450 MHz. The recommendation specifies a transmission power limit of 5 dBm for the 50 MHz bandplan and 8~dBm for the 100 MHz bandplan, therefore the maximum transmitted power in each carrier is the same for both bandplans. Due to the nature of an in-home wired environment, receivers that can handle both very large and very small amplitude signals are required; when transmitter and receiver are connected on the same electric outlet there is no channel attenuation and the signal-to-noise-plus-distortion ratio (SNDR) is dominated by the receiver linearity, whereas when transmitter and receiver are several rooms apart channel attenuation is high and the SNDR is dominated by the receiver noise figure. The high dynamic range specifications for these receivers require the use of configurable-gain topologies that can provide both high-linearity and low-noise for different configurations. Thus, this thesis has been aimed at researching high dynamic range broadband inductor-less topologies to be used as the RF front-end for a G.hn receiver complying with the provided specifications. A large part of the thesis has been focused on the design of the input amplifier of the front-end, which is the most critical stage as the noise figure and linearity of the input amplifier define the achievable overall specifications of the whole front-end. Three prototypes has been manufactured using a 65 nm CMOS process: two input RFPGAs and one front-end using the second RFPGA prototype.El "sistema en un chip" (SoC) fue adoptado recientemente como una de las soluciones para reducir el coste de sistemas integrados. Cuando se empezó a utilizar la solución SoC, el producto final era más caro debido al bajo rendimiento de producción. Los avances en tecnología integrada a lo largo de los años han permitido la integración de más componentes en menos área con mejoras en rendimiento. Por lo tanto, SoCs pasó a ser una solución ampliamente utilizada para reducir el coste del producto final, integrando en un único chip las principales partes de un sistema: analógica, digital y memoria. A medida que las tecnologías integradas se reducían en tamaño para permitir una mayor densisdad de transistores y proveer mayor funcionalidad con la misma área, las partes RF analógicas del SoC pasaron a ser la limitación en la reducción de costes ya que los inductores ocupan mucha área y no escalan con la tecnología. Por lo tanto, las tendencias en investigación se mueven hacia el diseño de SoCs sin inductores que todavía reducen más el coste final del producto. También, a medida que la demanda en sistemas de comunicación domésticos de alta velocidad ha crecido a lo largo de la última década, se han desarrollado varios estándares para satisfacer los requisitos de cada aplicación, siendo las redes sin hilos (WLANs) basadas en el estándar IEEE 802.11 las más populares. Sin embargo, una pobre propagación de señal a través de las paredes hacen que las WLANs sean inadecuadas para aplicaciones de alta-velocidad como transmisión de vídeo de alta definición en tiempo real, resultando en el desarrollo de tecnologías con hilos utilizando la infraestructura existente en los domicilios. La recomendación ITU-T G.hn (G.9960 and G.9961) unifica las principales infraestructuras con hilos domésticas (cables coaxiales, línias de teléfono y línias de electricidad) en un sólo estándar para la transmisión de datos hasta 1 Gb/s. La recomendación G.hn define una red unificada sobre línias de electricidad, de teléfono y coaxiales con diferentes esquemas para banda base y RF. El esquema RF-coax en el cual se basa esta tesis, usa canales con un ancho de banda de 50 MHz y 100 MHz con 256 y 512 portadoras respectivamente. La frecuencia centra puede variar desde 350 MHz hasta 2450 MHz. La recomendación especifica un límite en la potencia de transmisión de 5 dBm para el esquema de 50 MHz y 8 dBm para el esquema de 100 MHz, de tal forma que la potencia máxima por portadora es la misma en ambos esquemas. Debido a la estructura de un entorno doméstico con hilos, los receptores deben ser capaces de procesar señales con amplitud muy grande o muy pequeña; cuando transmisor y receptor están conectados en la misma toma eléctrica no hay atenuación de canal y el ratio de señal a rudio más distorsión (SNDR) está dominado por la linealidad del receptor, mientras que cuando transmisor y receptor están separados por varias habitaciones la atenuación es elevada y el SNDR está dominado por la figura de ruido del receptor. Los elevados requisitos de rango dinámico para este tipo de receptores requieren el uso de topologías de ganancia configurable que pueden proporcionar tanto alta linealidad como bajo ruido para diferentes configuraciones. Por lo tanto, esta tesis está encarada a la investigación de topologías sin inductores de banda ancha y elevado rango dinámico para ser usadas a la entrada de un receptor G.hn cumpliendo con las especificaciones proporcionadas. Una gran parte de la tesis se ha centrado en el diseño del amplificador de entrada al ser la etapa más crítica, ya que la figura de ruido y linealidad del amplificador de entrada definen lás máximas especificaciones que el sistema puede conseguir. Se han fabricado 3 prototipos con un proceso CMOS de 65 nm: 2 amplificadores y un sistema completo con amplificador y mezclador.Postprint (published version

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

CMOS Wide Tuning Gilbert Mixer with Controllable IF Bandwidth in Upcoming RF Front End for Multi-Band Multi-Standard Applications

The current global system for mobile communications, wireless local area, Bluetooth, and ultra-wideband demands a multi-band/multi-standard RF front end that can access all the available bandwidth specifications. Trade-offs occur between power consumption, noise figure, and linearity in CMOS Gilbert mixer wide tuning designs. Besides, it is preferable to have a constant IF bandwidth for different gain settings as the bandwidth varies with the load impedance when an RF receiver is tuned to a higher frequency. My dissertation consists of three parts. First, a tunable constant IF bandwidth Gilbert mixer is introduced for multi-band standard wireless applications such as 802.11 a/b/g WLAN and 802.16a WMAN, followed by a design synthesis approach to optimize the mixer to meet the design center frequency range, constant IF bandwidth, and power. A synthesized Gilbert mixer with effective prototype inductors, designed in 180 nm CMOS process, is presented in this dissertation with the tunability of 200 MHz IF, a constant IF bandwidth of 50 MHz, a conversion gain of 13.75 dB, a noise figure of 2.9dB, 1-dB compression point of -15.19 dBm, IIP3 of -5.8 dBm, and a power of 9 mW. Next, mixer inductor loss and equivalent electronic circuit analysis are presented to optimize the approach to offset center frequency and bandwidth inaccuracy due to the inductance loss between the actual and ideal prototype inductor. The proposed tunable Gilbert mixer simulations present a tunable IF of 177.8 MHz, an IF bandwidth of 87.57 MHz, a conversion gain of 7.4 dB, a noise figure of 3.14 dB, 1-dB compression point of -17.1 dBm, and IIP3 of -19.8 dBm. Last, a CMOS integrated wide frequency span CMOS low noise amplifier is integrated with the tunable Gilbert mixer to achieve a 27.68 dB conversion gain, a 3.47 dB low noise figure, -14.6 dBm 1-dB compression point, and -18.6 dBm IIP3

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

HIGH LINEARITY UNIVERSAL LNA DESIGNS FOR NEXT GENERATION WIRELESS APPLICATIONS

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design