9 research outputs found

    All-Digital Phase-Locked Loop for Radio Frequency Synthesis

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    It has been a constant challenge in wireless system design to meet the growing demand for an ever higher data rate and more diversified functionality at minimal cost and power consumption. The key lies in exploiting the phenomenal success of CMOS technology scaling for high-level integration. This underlies the paradigm shift in the field of integrated circuit (IC) design to one that increasingly favours digital circuits as opposed to their analog counterparts. With radio transceiver design for wireless systems in particular, a noticeable trend is the introduction of digital-intensive solutions for traditional analog functions. A prominent example is the emergence of the all-digital phase-locked loop (ADPLL) architectures for frequency synthesis. By avoiding traditional analog blocks, the ADPLL brings the benefits of high-level integration and improved programmability. This thesis presents ADPLL frequency synthesizer design, highlighting practical design considerations and technical innovations. Three prototype designs using a 65-nm CMOS technology are presented. The first example address a low-power ADPLL design for 2.4-GHz ISM (Industrial, Scientific, Medical) band frequency synthesis. A high-speed topology is employed in the implementation for the variable phase accumulator to count full cycles of the radio frequency (RF) output. A simple technique based on a short delay line in the reference signal path allows the time-to-digital converter (TDC) core to operate at a low duty cycle with approximately 95% reduction in its average power consumption. The ADPLL incorporates a two-point modulation scheme with an adaptive gain calibration to allow for direct frequency modulation. The second implementation is a wide-band ADPLL-based frequency synthesizer for cognitive radio sensor units. It employs a digitally controlled ring oscillator with an LC tank introduced to extend the tuning range and reduce power dissipation. An adaptive frequency calibration technique based on binary search is used for fast frequency settling. The third implementation is another wideband ADPLL frequency synthesizer. At the architectural level, separation of coarse-tune and fine-tune branches results in a word length reduction for both of them and allows the coarse tuning logic to be powered off or clock gated during normal operation, which led to a significant reduction in the area and power consumption for the digital logic and simplified the digital design. A dynamic binary search technique was proposed to achieve further improved frequency calibration speed compared with previous techniques. In addition, an original technique was employed for the frequency tuning of the wideband ring oscillator to allow for compact design and excellent linearity

    High Tolerance of Charge Pump Leakage Current in Integer-N PLL Frequency Synthesizer for 5G Networks

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    One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81-86] GHz using ultra-wide channel spacing of 1GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved

    Design of energy efficient high speed I/O interfaces

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    Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

    A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL)

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    Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area. In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF). The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz

    Quantifying, generating and mitigating radio interference in Low-Power Wireless Networks

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    Doctoral Programme in Telecommunication - MAP-teleRadio interference a ects the performance of low-power wireless networks (LPWN), leading to packet loss and reduced energy-e ciency, among other problems. Reliability of communications is key to expand application domains for LPWN. Since most LPWN operate in the license-free Industrial Scienti c and Medical (ISM) bands and hence share the spectrum with other wireless technologies, addressing interference is an important challenge. In this context, we present JamLab: a low-cost infrastructure to augment existing LPWN testbeds with accurate interference generation in LPWN testbeds, useful to experimentally investigate the impact of interference on LPWN protocols. We investigate how interference in a shared wireless medium can be mitigated by performing wireless channel energy sensing in low-cost and low-power hardware. For this pupose, we introduce a novel channel quality metric|dubbed CQ|based on availability of the channel over time, which meaningfully quanti es interference. Using data collected from a number of Wi-Fi networks operating in a library building, we show that our metric has strong correlation with the Packet Reception Rate (PRR). We then explore dynamic radio resource adaptation techniques|namely packet size and error correction code overhead optimisations|based on instantaneous spectrum usage as quanti ed by our CQ metric. To conclude, we study emerging fast fading in the composite channel under constructive baseband interference, which has been recently introduced in low-power wireless networks as a promising technique. We show the resulting composite signal becomes vulnerable in the presence of noise, leading to signi cant deterioration of the link, whenever the carriers have similar amplitudes. Overall, our results suggest that the proposed tools and techniques have the potential to improve performance in LPWN operating in the unlicensed spectrum, improving coexistence while maintaining energy-e ciency. Future work includes implementation in next generation platforms, which provides superior computational capacity and more exible radio chip designs.A interferência de r adio afeta o desempenho das redes de comunicação sem o de baixo consumo - low-power wireless networks (LPWN), o que provoca perdas de pacotes, diminuição da e ciência energética, entre outros problemas. A contabilidade das comunicações e importante para a expansão e adoção das LPWN nos diversos domínios de potencial aplicação. Visto que a grande maioria das LPWN partilham o espectro radioelétrico com outras redes sem o, a interferência torna-se um desafio importante. Neste contexto, apresentamos o JamLab: uma infraestrutura de baixo custo para estender a funcionalidade dos ambientes laboratoriais para o estudo experimental do desempenho das LPWN sob interferência. Resultando, assim, numa ferramenta essencial para a adequada verificação dos protocolos de comunicações das LPWN. Para al em disso, a Tese introduz uma nova técnica para avaliar o ambiente radioelétrico e demostra a sua utilização para gerir recursos disponíveis no transceptor rádio, o que permite melhorar a fiabilidade das comunicações, nomeadamente nas plataformas de baixo consumo, garantindo e ciência energética. Assim, apresentamos uma nova métrica| denominada CQ - concebida especificamente para quantificar a qualidade do canal r adio, com base na sua disponibilidade temporal. Mediante dados adquiridos em v arias redes sem o Wi-Fi, instaladas no edifício de uma biblioteca universitária, demonstra-se que esta métrica tem um ótimo desempenho, evidenciando uma elevada correlação com a taxa de receção de pacotes. Investiga-se ainda a potencialidade da nossa métrica CQ para gerir dinamicamente recursos de radio como tamanho de pacote e taxa de correlação de erros dos códigos - baseado em medições instantâneas da qualidade do canal de radio. Posteriormente, estuda-se um modelo de canal composto, sob interferência construtiva de banda-base. A interferência construtiva de banda-base tem sido introduzida recentemente nas LPWN, evidenciando ser uma técnica prometedora no que diz respeito à baixa latência e à contabilidade das comunicações. Na Tese investiga-se o caso crítico em que o sinal composto se torna vulnerável na presença de ruído, o que acaba por deteriorar a qualidade da ligação, no caso em que as amplitudes das distintas portadoras presentes no receptor sejam similares. Finalmente, os resultados obtidos sugerem que as ferramentas e as técnicas propostas têm potencial para melhorar o desempenho das LPWN, num cenário de partilha do espectro radioelétrico com outras redes, melhorando a coexistência e mantendo e ciência energética. Prevê-se como trabalho futuro a implementação das técnicas propostas em plataformas de próxima geração, com maior flexibilidade e poder computacional para o processamento dos sinais rádio.This work was supported by FCT (Portuguese Foundation for Science and Technology) and by ESF (European Social Fund) through POPH (Portuguese Human Potential Operational Program), under PhD grant SFRH/BD/62198/2009; also by FCT under project ref. FCOMP-01-0124-FEDER-014922 (MASQOTS), and EU through the FP7 programme, under grant FP7-ICT-224053 (CONET)

    Jitter reduction techniques for digital audio.

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    by Tsang Yick Man, Steven.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 94-99).ABSTRACT --- p.iACKNOWLEDGMENT --- p.iiLIST OF GLOSSARY --- p.iiiChapter 1 --- INTRODUCTION --- p.1Chapter 1.1 --- What is the jitter ? --- p.3Chapter 2 --- WHY DOES JITTER OCCUR IN DIGITAL AUDIO ? --- p.4Chapter 2.1 --- Poorly-designed Phase Locked Loop ( PLL ) --- p.4Chapter 2.1.1 --- Digital data problem --- p.7Chapter 2.2 --- Sampling jitter or clock jitter ( Δti) --- p.9Chapter 2.3 --- Waveform distortion --- p.12Chapter 2.4 --- Logic induced jitter --- p.17Chapter 2.4.1 --- Digital noise mechanisms --- p.20Chapter 2.4.2 --- Different types of D-type flop-flip chips are linked below for ease of comparison --- p.21Chapter 2.4.3 --- Ground bounce --- p.22Chapter 2.5 --- Power supply high frequency noise --- p.23Chapter 2.6 --- Interface Jitter --- p.25Chapter 2.7 --- Cross-talk --- p.28Chapter 2.8 --- Inter-Symbol-Interference (ISI) --- p.28Chapter 2.9 --- Baseline wander --- p.29Chapter 2.10 --- Noise jitter --- p.30Chapter 2.11 --- FIFO jitter reduction chips --- p.31Chapter 3 --- JITTER REDUCTION TECHNIQUES --- p.33Chapter 3.1 --- Why using two-stage phase-locked loop (PLL ) ?Chapter 3.1.1 --- The PLL circuit components --- p.35Chapter 3.1.2 --- The PLL timing specifications --- p.36Chapter 3.2 --- Analog phase-locked loop (APLL ) circuit usedin second stage --- p.38Chapter 3.3 --- All digital phase-locked loop (ADPLL ) circuit used in second stage --- p.40Chapter 3.4 --- ADPLL design --- p.42Chapter 3.4.1 --- "Different of K counter value of ADPLL are listed for comparison with M=512, N=256, Kd=2" --- p.46Chapter 3.4.2 --- Computer simulated results and experimental results of the ADPLL --- p.47Chapter 3.4.3 --- PLL design notes --- p.58Chapter 3.5 --- Different of the all digital Phase-Locked Loop (ADPLL ) and the analogue Phase-Locked Loop (APLL ) are listed for comparison --- p.65Chapter 3.6 --- Discrete transistor oscillator --- p.68Chapter 3.7 --- Discrete transistor oscillator circuit operation --- p.69Chapter 3.8 --- The advantage and disadvantage of using external discrete oscillator --- p.71Chapter 3.9 --- Background of using high-precision oscillators --- p.72Chapter 3.9.1 --- The temperature compensated crystal circuit operation --- p.73Chapter 3.9.2 --- The temperature compensated circuit design notes --- p.75Chapter 3.10 --- The discrete voltage reference circuit operation --- p.76Chapter 3.10.1 --- Comparing the different types of Op-amps that can be used as a voltage comparator --- p.79Chapter 3.10.2 --- Precaution of separate CMOS chips Vdd and Vcc --- p.80Chapter 3.11 --- Board level jitter reduction method --- p.81Chapter 3.12 --- Digital audio interface chips --- p.82Chapter 3.12.1 --- Different brand of the digital interface receiver (DIR) chips and clock modular are listed for comparison --- p.84Chapter 4. --- APPLICATION CIRCUIT BLOCK DIAGRAMS OF JITTER REDUCTION AND CLOCK RECOVERY --- p.85Chapter 5 --- CONCLUSIONS --- p.90Chapter 5.1 --- Summary of the research --- p.90Chapter 5.2 --- Suggestions for further development --- p.92Chapter 5.3 --- Instrument listing that used in this thesis --- p.93Chapter 6 --- REFERENCES --- p.94Chapter 7 --- APPENDICES --- p.100Chapter 7.1.1 --- Phase instability in frequency dividersChapter 7.1.2 --- The effect of clock tree on Tskew on ASIC chipChapter 7.1.3 --- Digital audio transmission----Why jitter is important?Chapter 7.1.4 --- Overview of digital audio interface data structuresChapter 7.1.5 --- Typical frequency Vs temperature variations curve of Quartz crystalsChapter 7.2 --- IC specification used in these research projec

    Proceedings of the Sixteenth Annual Precise Time and Time Interval (PTTI) Applications and Planning Meeting

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    The effects of ionospheric and tropospheric propagation on time and frequency transfer, advances in the generation of precise time and frequency, time transfer techniques and filtering and modeling were among the topics emphasized. Rubidium and cesium frequency standard, crystal oscillators, masers, Kalman filters, and atomic clocks were discussed

    Large space structures and systems in the space station era: A bibliography with indexes (supplement 05)

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    Bibliographies and abstracts are listed for 1363 reports, articles, and other documents introduced into the NASA scientific and technical information system between January 1, 1991 and July 31, 1992. Topics covered include technology development and mission design according to system, interactive analysis and design, structural and thermal analysis and design, structural concepts and control systems, electronics, advanced materials, assembly concepts, propulsion and solar power satellite systems
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