Hard macrocells for DC/DC converter in automotive embedded mechatronic systems

A novel configurable DC/DC converter architecture, to be integrated as hard macrocell in automotive embedded systems, is proposed in the paper. It aims at realizing an intelligent voltage regulator. With respect to the state of the art, the challenge is the integration into an automotive-qualified chip of several advanced features like dithering of switching frequency, nested control loops with both current and voltage feedback, asynchronous hysteretic control for low power mode, slope control of the power FET gate driver, and diagnostic block against out-of-range current or voltage or temperature conditions. Moreover, the converter macrocell can be connected to the in-vehicle digital network, exchanging with the main vehicle control unit status/diagnostic flags and commands. The proposed design can be configured to work both in step-up and step-down modes, to face a very wide operating input voltage range from 2.5 to 60 V and absolute range from −0.3 to 70 V. The main target is regulating all voltages required in the emerging hybrid/electric vehicles where, besides the conventional 12 V DC bus, also a 48 V DC bus is present. The proposed design supports also digital configurability of the output regulated voltage, through a programmable divider, and of the coefficients of the proportional-integrative controller inside the nested control loops. Fabricated in 0.35 μm CMOS technology, experimental measurements prove that the IC can operate in harsh automotive environments since it meets stringent requirements in terms of electrostatic discharge (ESD) protection, operating temperature range, out-of-range current, or voltage condition

Universal Programmable Battery Charger with Optional Battery Management System

This report demonstrates improvements made in battery charging and battery management technology through the design of a universal programmable battery charger with optional battery management system attachment. This charger offers improvements in charge efficiency and unique battery charging algorithms to charge a variety of battery chemistries with variety of power requirements. Improvements in efficiency result from a synchronous Buck Controller topology as compared to previous universal chargers that use asynchronous Buck-Boost Converter topologies. This battery charger also surpasses current universal battery chargers by offering different charge modes for different battery chemistries. Charge modes provide the user an option between extending the life of the battery by selecting a mode with a slower, less stressful charge rate or a shorter charge time with a fast, more stressful charging mode. The user can also choose a charge mode in which the battery charges to full capacity, resulting in maximum runtime or a less than full capacity, which puts less stress on the battery thus extending the lifetime. Ultimately, this system permits weighing the performance tradeoff of battery lifetime and charge time. The optional battery management system attachment offers more precise monitoring of each cell and cell balancing for Li-Ion batteries. This further enhances the performance of the charger when integrated, but is not necessary for charger operation. The battery charger consists of three subcircuits: A microcontroller unit, a power stage, and a current sensing circuit. A C2000 Piccolo F28069 microcontroller controls a LM5117 Buck Controller by injecting a pulse-width modulated signal into the feedback node controlling the output of the buck to set a constant current or constant voltage thus creating a programmable battery charger. The pulse-width modulated signal changes according to charge algorithms created in software for specific battery chemistries and charge requirements. An analog-to-digital converter on the microcontroller monitors battery voltage by using a voltage divider and an INA169 current shunt monitor, which outputs a voltage corresponding to the charge current to another analog-to-digital converter on the microcontroller, monitors the charge current. This allows the charger program to maintain correct and safe charging conditions for each charge mode in addition to measuring output power. Lights on the microcontroller display a real-time status to the user of which portion of the charge profile the charger is in. A solid red light means the charger is in the constant current portion of the charge profile. A blinking red light means the charger is in the constant voltage portion. No red light means the battery charger finished and the battery is currently charged above nominal voltage. The battery charger works with the battery management system in the next section to provide ultimate battery charging and managing capabilities. The battery management system consists of two subcircuits: A microcontroller and a battery monitoring circuit. The MSP430FR5969 microcontroller unit communicates with BQ76PL536 battery management integrated circuits to create a battery management system that monitors data such as cell voltage, pack voltage, pack temperature, state of charge, fault statuses, alert statuses, and a variety of other useful cell parameters. This data displays on a liquid crystal display screen through different menu options. The user scrolls through the menus using a capacitive touch slider on the microcontroller unit and selects a given option using the option select button. A cell balance mode allows the user to check the balance of the cells and allows cell balancing if the cells differ by more than a set threshold

A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Low jitter phase-locked loop clock synthesis with wide locking range

The fast growing demand of wireless and high speed data communications has driven efforts to increase the levels of integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase noise for communications systems which employ a phase-locked loop for frequency and clock synthesis with on-chip VCO. This dictates an integrated CMOS implementation of the VCO with very low phase noise performance. The ring oscillator VCOs based on differential delay cell chains have been used successfully in communications applications, but thermal noise induced phase noise have to be minimized in order not to limit their applicability to some applications which impose stringent timing jitter and phase noise requirements on the PLL clock synthesizer. Obtaining lower timing jitter and phase noise at the PLL output also requires the minimization of noise in critical circuit design blocks as well as the optimization of the loop bandwidth of the PLL. In this dissertation the fundamental performance limits of CMOS PLL clock synthesizers based on ring oscillator VCOs are investigated. The effect of flicker and thermal noise in MOS transistors on timing jitter and phase noise are explored, with particular emphasis on source coupled NMOS differential delay cells with symmetric load elements. Several new circuit architectures are employed for the charge pump circuit and phase-frequency detector (PFD) to minimize the timing jitter due to the finite dead zone in the PFD and the current mismatch in the charge pump circuit. The selection of the optimum PLL loop bandwidth is critical in determining the phase noise performance at the PLL output. The optimum loop bandwidth and the phase noise performance of the PLL is determined using behavioral simulations. These results are compared with transistor level simulated results and experimental results for the PLL clock synthesizer fabricated in a 0.35 µm CMOS technology with good agreement. To demonstrate the proposed concept, a fully integrated CMOS PLL clock synthesizer utilizing integer-N frequency multiplier technique to synthesize several clock signals in the range of 20-400 MHz with low phase noise was designed. Implemented in a standard 0.35-µm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps (rms) and 38-ps (peak-to-peak) at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The specific research contributions of this work include (1) proposing, designing, and implementing a new charge pump circuit architecture that matches current levels and therefore minimizes one source of phase noise due to fluctuations in the control voltage of the VCO, (2) an improved phase-frequency detector architecture which has improved characteristics in lock condition, (3) an improved ring oscillator VCO with excellent thermal noise induced phase noise characteristics, (4) the application of selfbiased techniques together with fixed bias to CMOS low phase noise PLL clock synthesizer for digital video communications ,and (5) an analytical model that describes the phase noise performance of the proposed VCO and PLL clock synthesizer

A Low Total Harmonic Distortion Sinusoidal Oscillator Based on Digital Harmonic Cancellation Technique

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe