SoK: Design Tools for Side-Channel-Aware Implementations

Side-channel attacks that leak sensitive information through a computing device's interaction with its physical environment have proven to be a severe threat to devices' security, particularly when adversaries have unfettered physical access to the device. Traditional approaches for leakage detection measure the physical properties of the device. Hence, they cannot be used during the design process and fail to provide root cause analysis. An alternative approach that is gaining traction is to automate leakage detection by modeling the device. The demand to understand the scope, benefits, and limitations of the proposed tools intensifies with the increase in the number of proposals. In this SoK, we classify approaches to automated leakage detection based on the model's source of truth. We classify the existing tools on two main parameters: whether the model includes measurements from a concrete device and the abstraction level of the device specification used for constructing the model. We survey the proposed tools to determine the current knowledge level across the domain and identify open problems. In particular, we highlight the absence of evaluation methodologies and metrics that would compare proposals' effectiveness from across the domain. We believe that our results help practitioners who want to use automated leakage detection and researchers interested in advancing the knowledge and improving automated leakage detection

6502 emulator on FPGA

6502 microprocessor was once used in almost all of the microcomputer in the 80s, including the Apple II lines of computer, the Commodore PET, the Commodore 64, the Atari 8-bit series and even on the Nintendo Entertainment System (NES) video game console. The objective of this project is to emulate the once famous 6502 microprocessor onto a FPGA chip. The FPGA-based 6502 microprocessor had to emulate the functionality of a real 6502 microprocessor. Accurate pinouts emulation is desired but not a must. The 6502 assembly language is easy to learn and building a computer based on this microprocessor requires very few parts, thus making this project a great experiential learning process. The scope of this project requires the student to have an in-depth understanding on computer system architecture, especially on 6502 architecture; V erilog to understand existing 6502 source code from Bird Computer and also FPGA development process (synthesis tools) to transfer the Verilog code to the FPGA chip. Thus far, the resources and information on 6502 microprocessor looks promising. The student earlier scope was to come up with the 6502 code in Verilog HDL, but as there is available code from Bird Computer (State Machine coded) so the student had chanced his objectives to understand the existing code and implement it on FPGA only. But as along the way, problems occur on hardware implementation, focus had been switched again to simulate the existing code or ALU or simple processor to build up student understanding and for documentation for future project expansion. To test the functionality of the 6502 system, the student will either find existing application or come up with simple program to run using the FPGA-based 6502 system

MOCAST 2021

The 10th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2021) will take place in Thessaloniki, Greece, from July 5th to July 7th, 2021. The MOCAST technical program includes all aspects of circuit and system technologies, from modeling to design, verification, implementation, and application. This Special Issue presents extended versions of top-ranking papers in the conference. The topics of MOCAST include:Analog/RF and mixed signal circuits;Digital circuits and systems design;Nonlinear circuits and systems;Device and circuit modeling;High-performance embedded systems;Systems and applications;Sensors and systems;Machine learning and AI applications;Communication; Network systems;Power management;Imagers, MEMS, medical, and displays;Radiation front ends (nuclear and space application);Education in circuits, systems, and communications

Grid fault ride through for wind turbine doubly-fed induction generators

EngD ThesisWind farms must contribute to the stability and reliability of the transmission grid, if they are to form a robust component of the electrical network. This includes providing grid support during grid faults, or voltage dips. Transmission system grid codes require wind farms to remain connected during specified voltage dips, and to supply active and reactive power into the network. Doubly-fed induction generator (DFIG) technology is presently dominant in the growing global market for wind power generation, due to the combination of variable-speed operation and a cost-effective partially-rated power converter. However, the DFIG is sensitive to dips in supply voltage. Without specific protection to 'ride through' grid faults a DFIG risks damage to its power converter due to over-current and/or overvoltage. Conventional converter protection via a sustained period of rotor-crowbar closed-circuit leads to poor power output and sustained suppression of the stator voltages. This thesis presents a detailed understanding of wind turbine DFIG grid fault response, including flux linkage behaviour and magnetic drag effects. A flexible 7.5kW test facility is used to validate the description of fault response and evaluate techniques for improving fault ride-through performance. A minimum threshold rotor crowbar method is presented, successfully diverting transient over-currents and restoring good power control within 45ms of both fault initiation and clearance. Crowbar application periods were reduced to 11-16ms. A study of the maximum crowbar resistance suggests that this method can be used with high-power DFIG turbines. Alternatively, a DC-link brake method is shown to protect the power converter and quench the transient rotor currents, allowing control to be resumed; albeit requiring 100ms to restore good control. A VAr-support control scheme reveals a 14% stator voltage increase in fault tests: reducing the step-voltage impact at fault clearance and potentially assisting the fault response of other local equipment.EPSR