A Generalized Scalar Potential Integral Equation Formulation for the DC Analysis of Conductors

The electrostatic modeling of conductors is a fundamental challenge in various applications, including the prediction of parasitic effects in electrical interconnects, the design of biasing networks, and the modeling of biological, microelectromechanical, and sensing systems. The boundary element method (BEM) can be an effective simulation tool for these problems because it allows modeling three-dimensional objects with only a surface mesh. However, existing BEM formulations can be restrictive because they make assumptions specific to particular applications. For example, capacitance extraction formulations usually assume a constant electric scalar potential on the surface of each conductor and cannot be used to model a flowing current, nor to extract the resistance. When modeling steady currents, many existing techniques do not address mathematical challenges such as the null space associated with the operators representing the internal region of a conductor. We propose a more general BEM framework based on the electric scalar potential for modeling conductive objects in various scenarios in a unified manner. Restrictive application-specific assumptions are not made, and the aforementioned operator null space is handled in an intuitive and rigorous manner. Numerical examples drawn from diverse applications confirm the accuracy and generality of the proposed method.Comment: 12 pages, 13 figures. Submitted to the IEEE Transactions on Antennas and Propagatio

Fast methods for full-wave electromagnetic simulations of integrated circuit package modules

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.Ph.D.Committee Chair: Swaminathan Madhavan; Committee Member: Papapolymerou John; Committee Member: Chatterjee Abhijit; Committee Member: Peterson Andrew; Committee Member: Sitaraman Sures

MULTISCALE EXAMINATION AND MODELING OF ELECTRON TRANSPORT IN NANOSCALE MATERIALS AND DEVICES

For half a century the integrated circuits (ICs) that make up the heart of electronic devices have been steadily improving by shrinking at an exponential rate. However, as the current crop of ICs get smaller and the insulating layers involved become thinner, electrons leak through due to quantum mechanical tunneling. This is one of several issues which will bring an end to this incredible streak of exponential improvement of this type of transistor device, after which future improvements will have to come from employing fundamentally different transistor architecture rather than fine tuning and miniaturizing the metal-oxide-semiconductor field effect transistors (MOSFETs) in use today. Several new transistor designs, some designed and built here at Michigan Tech, involve electrons tunneling their way through arrays of nanoparticles. We use a multi-scale approach to model these devices and study their behavior. For investigating the tunneling characteristics of the individual junctions, we use a first-principles approach to model conduction between sub-nanometer gold particles. To estimate the change in energy due to the movement of individual electrons, we use the finite element method to calculate electrostatic capacitances. The kinetic Monte Carlo method allows us to use our knowledge of these details to simulate the dynamics of an entire device— sometimes consisting of hundreds of individual particles—and watch as a device ‘turns on’ and starts conducting an electric current. Scanning tunneling microscopy (STM) and the closely related scanning tunneling spectroscopy (STS) are a family of powerful experimental techniques that allow for the probing and imaging of surfaces and molecules at atomic resolution. However, interpretation of the results often requires comparison with theoretical and computational models. We have developed a new method for calculating STM topographs and STS spectra. This method combines an established method for approximating the geometric variation of the electronic density of states, with a modern method for calculating spin-dependent tunneling currents, offering a unique balance between accuracy and accessibility

Thermal and performance modeling of nanoscale mosfets, carbon nanotube devices and integrated circuits

We offer new paradigms for electronic devices and digital integrated circuits (ICs) in an effort to overcome important performance threatening problems such as self heating. To investigate chip heating, we report novel methods for predicting the thermal profiles of complex ICs at the resolution of a single device. We resolve device and IC temperatures self-consistently, with individual device performances, while accounting for IC layout and software application details. At the device level, we calculate performance and generated heat details. We then extend these performance figures to the overall chip using a stochastic or Monte Carlo type methodology. Next, at the IC level, we solve for the device temperatures using the chip's layout and application software details. Here, we apply our mixed-mode algorithm to two-dimensional (planar) and three-dimensional ICs. To relieve thermal stresses and performance degradation in specific areas of extreme heating or hot spots, we offer design strategies using thermal contacts or different IC layouts. Moreover, we also show chips that we had designed and fabricated through IC fabrication clearing house MOSIS for experimental investigations. We also investigate carbon nanotubes (CNTs) and CNT embedded MOSFETs as new device paradigms for future electronic circuits. To examine the effects of CNTs on device performance, we develop a CNT Monte Carlo simulator, and determine scattering rates and CNT electron transport. Here, we report position-dependent velocity oscillations and length effects in semiconducting single-walled zig-zag carbon nanotubes. Our calculated results indicate velocity oscillations in the Terahertz range, which approaches phonon frequencies. This may facilitate new high frequency RF device and circuit designs, opening new paradigms in communication networks. Furthermore, to obtain device performance figures for MOSFETs that embed CNTs in their channels, our device solver determines interactions between the CNT and silicon (Si) by obtaining quantization and transport effects on the tube and the Si, and at the CNT-Si barrier. We predict that the CNT-MOSFET yields a better performance than the traditional MOSFET. Especially, CNT-MOSFETs employing lower diameter tubes exhibit improved performance capabilities. We also perform similar analyses for CNT embedded SOI-MOSFETs