On issues of equalization with the decorrelation algorithm : fast converging structures and finite-precision

To increase the rate of convergence of the blind, adaptive, decision feedback equalizer based on the decorrelation criterion, structures have been proposed which dramatically increase the complexity of the equalizer. The complexity of an algorithm has a direct bearing on the cost of implementing the algorithm in either hardware or software. In this thesis, more computationally efficient structures, based on the fast transversal filter and lattice algorithms, are proposed for the decorrelation algorithm which maintain the high rate of convergence of the more complex algorithms. Furthermore, the performance of the decorrelation algorithm in a finite-precision environment will be studied and compared to the widely used LMS algorithm

Digital processing of signals in the presence of inter-symbol interference and additive noise

Imperial Users onl

Adaptive equalizers and the DFE

L’argomento principale che viene affrontato nella tesina è quello dell’equalizzatore DFE; ne viene spiegata la struttura e la funzionalità. In particolar modo viene affrontato il problema del calcolo dei coefficienti dei filtri che lo compongono. Questi infati possono essere calcolati tramite metodo direto che però richiede l’inversione della matrice delle autocorrelazioni R e questo richiede una complessità di realizzazione elevata. Per semplificare questa complessità si introduce la fattorizzazione di Cholesky della matrice R che abbassa di grado la complessitàope

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS

An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-μm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented

Performance comparison of blind and non-blind channel equalizers using artificial neural networks

In digital communication systems, multipath propagation induces Inter Symbol Interference (ISI). To reduce the effect of ISI different channel equalization algorithms are used. Complex equalization algorithms allow for achieving the best performance but they do not meet the requirements for implementation of real-time detection at low complexity, thus limiting their application. In this paper, we present different blind and non-blind equalization structures based on Artificial Neural Networks (ANNs) and, also, we analyze their complexity versus performance. Since the activation function at the output layer depends on the cost function with respect to the input, in the present work we use mean squared error as loss function for the output layer. The simulated network is based on multilayer feedforward perceptron ANN, which is trained by utilizing the error back-propagation algorithm. The weights of the network are updated in accordance with training of the network to improve the convergence speed. Simulation results demonstrate that the implementation of equalizers using ANN provides an upper hand over the performance and computational complexity with respect to conventional methods