Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

Multi-objective optimal design of obstacle-avoiding two-dimensional Steiner trees with application to ascent assembly engineering.

We present an effective optimization strategy that is capable of discovering high-quality cost-optimal solution for two-dimensional (2D) path network layouts (i.e., groups of obstacle-avoiding Euclidean Steiner trees) that, among other applications, can serve as templates for complete ascent assembly structures (CAA-structures). The main innovative aspect of our approach is that our aim is not restricted to simply synthesizing optimal assembly designs with regard to a given goal, but we also strive to discover the best trade-offs between geometric and domain-dependent optimal designs. As such, the proposed approach is centred on a variably constrained multi-objective formulation of the optimal design task and on an efficient co-evolutionary solver. The results we obtained on both artificial problems and realistic design scenarios based on an industrial test case empirically support the value of our contribution to the fields of optimal obstacle-avoiding path generation in particular and design automation in general

Interconnect optimizations for nanometer VLSI design

textAs the semiconductor technology scales into deeper sub-micron domain, billions of transistors can be used on a single system-on-chip (SOC) makes interconnection optimization more important roughly for two reasons. First, congestion, power, timing in routing and buffering requirements make inter- connection optimization more and more challenging. Second, gate delay get- ting shorter while the RC delay gets longer due to scaling. Study of interconnection construction and optimization algorithms in real industry flows and designs ends up with interesting findings. One used to be overlooked but very important and practical problem is how to utilize over- the-block routing resources intelligently. Routing over large IP blocks needs special attention as there is almost no way to insert buffers inside hard IP blocks, which can lead to unsolvable slew/timing violations. In current design flows we have seen, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. To handle that, this work proposes a novel buffering-aware over-the- block rectilinear Steiner minimum tree (BOB-RSMT) algorithm which helps reclaim the “wasted” over-the-block routing resources while meeting user-specified slew constraints. Proposed algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire-length. Moreover, due to the fact that timing optimization is important for the VLSI design, in this work, timing-driven over-the-block rectilinear Steiner tree (TOB-RST) is also studied to optimize critical paths. This proposed TOB-RST algorithm can be used in routing or post-routing stage to provide high-quality topologies to help close timing. Then a follow-up problem emerges: how to accomplish the whole routing with over-the-block routing resources used properly. Utilizing over-the- block routing resources could dramatically improve the routing solution, yet require special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. A new global router, BOB-Router, is to solve the over-the-block global routing problem through minimizing overflows, wire-length and via count simultaneously without violating slew constraints. Based on my completed works, BOB-RSMT and BOB-Router tremendously improve the overall routing and buffering quality. Experimental results show that proposed over-the-block rectilinear Steiner tree construction and routing completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding rectilinear Steiner tree construction and routing in terms of wire-length, via count and overflows.Electrical and Computer Engineerin

Interconnect tree optimization algorithm in nanometer very large scale integration designs

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power dissipation of the inserted buffers is another metric that needs to be optimized. Research has shown that power dissipation overhead due to buffer insertions is significantly high. In other words, interconnect delay and power dissipation move in opposite directions. Although many methodologies to optimize timing performance with power constraint have been proposed, no algorithm is based on grid graph technique. Hence, the main contribution of this thesis is an efficient algorithm using a hybrid approach for multi-constraint optimization in multi-terminal nets. The algorithm uses dynamic programming to compute the interconnect delay and power dissipation of the inserted buffers incrementally, while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multi-constraint optimizations and produces up to 47% better solution compared to a post routing buffer insertion algorithm in comparable runtime

Approximation Algorithms for Network Design Problems

We consider different variants of network design problems. Given a set of points in the plane we search for a shortest interconnection of them. In this general formulation the problem is known as Steiner tree problem. We consider the special case of octilinear Steiner trees in the presence of hard and soft obstacles. In an octilinear Steiner tree the line segments connecting the points are allowed to run either in horizontal, vertical or diagonal direction. An obstacle is a connected region in the plane bounded by a simple polygon. No line segment of an octilinear Steiner tree is allowed to lie in the interior of a hard obstacle. If we intersect a Steiner tree with the interior of a soft obstacle, no connected component of the induced subtree is allowed to be longer than a given fixed length. We provide polynomial time approximation schemes for the octilinear Steiner tree problem in the presence of hard and soft obstacles. These were the first presented approximation schemes introduced for the problems. Additionally, we introduce a (2+epsilon)-approximation algorithm for soft obstacles. We then turn to Euclidean group Steiner trees. Instead of a set of fixed points we get for each point a set of potential locations (combined into groups) and we need to pick only one location of each group. The groups we consider lie inside disjoint regions fulfilling a special property so-called alpha-fatness. Roughly speaking, the term alpha-fat specifies the shape of the region in comparison to a disk. We give the first approximation algorithm for this problem and achieve an approximation ratio of (1+epsilon)(9.093alpha +1). Last, we consider Manhattan networks. They are allowed to contain edges only in horizontal and vertical direction. In contrast to Steiner trees they contain a shortest path between each pair of points. We introduce insights into the structure of Manhattan networks, particularly in the context of so-called staircases. We give three new approximation algorithms for the Manhattan network problem, the first with approximation ratio 3 and two algorithms with ratio 2. To this end we introduce two algorithms for the Manhattan network problem of staircases. The first algorithm solves the problem to optimality the second yields a 2-approximation. Variants of both algorithms are already known in the literature. Since we use a slightly different definition of staircases and we need special properties of them, we adopt the algorithms to our situation. The 2-approximation algorithms achieve the best known approximation ratio of an algorithm for the Manhattan network problem known so far. Last we give an idea how we could possibly find an algorithm with better approximation ratio

Stacker crane problem state space reduction

Many resource delivery problems, from delivery vehicle routing to circuit board assembly, can be expressed as stacker-crane problems (SCPs). In SCPs, a single agent must transfer resources from their starting locations to goal locations by traversing a graph. These problems have been split into many categories based on their graph structure and other problem properties. This thesis examines preemptive stacker-crane problems on four-connected grids, which are common graphs in motion planning domains. A wealth of research has already been done on motion planning on graphs, both for optimal and suboptimal solutions. This thesis focuses on reducing the number of vertices in the graph and the number of actions available at each vertex rather than presenting a specific solution, which allows for any solver to be used on the reduced graph

Design Rules in VLSI Routing

One of the last major steps in the design of highly integrated circuits (VLSI design) is routing. The task of routing is to compute disjoint sets of wires connecting different parts of a chip in order to realize the desired electrical connectivity. Design rules define restrictions on the minimum distance and geometry of metal shapes. The intent of most design rules is to forbid patterns that cannot be manufactured well in the lithographic production process. This process has become extremely difficult with the current small feature sizes of 32 nm and below, which are still being manufactured using 193 nm wavelength technology. Because of this, the design rules of modern technologies have become very complex, and computing a routing with a sufficiently low number of design rule violations is a difficult task for automated routing tools. In this thesis we present in detail how design rules can be handled efficiently. We develop an appropriate design rule model which considerably reduces complexity while not being too restrictive. This involves mapping complex polygon-based rules to simpler rectangle-based rules and building equivalence classes of shapes with respect to their minimum distance requirements. Our model enables efficient checking of minimum distance rules, which has to be done dozens of times in each routing run. We also discuss efficient data structures that are necessary to achieve this. We implemented our design rule model within BonnRoute, the routing tool of the BonnTools, a software package for VLSI physical design developed at the Research Institute for Discrete Mathematics at the University of Bonn in cooperation with IBM. The result is a new module of BonnRoute, called BonnRoutRules, which computes this design rule model and embeds BonnRoute in the complex routing environment of current technologies. The BonnRouteRules module was a key part in enabling BonnRoute to route current 32 nm and 22 nm chips. We describe the combined routing flow used by IBM in practice, in which BonnRoute solves the main routing task and an industrial standard router is used for postprocessing. We present detailed experimental results of this flow on real-world designs. The results show that this combined flow produces routings with almost no remaining design rule violations, which proves that our design rule model works well in practice. Furthermore, compared to the industrial standard router alone, the combination with BonnRoute provides several significant benefits: It has 24% less runtime, 5% less wiring length, and over 90% less detours, which shows that with this flow we have an excellent routing tool in practice

Timing-Constrained Global Routing with Buffered Steiner Trees

This dissertation deals with the combination of two key problems that arise in the physical design of computer chips: global routing and buffering. The task of buffering is the insertion of buffers and inverters into the chip's netlist to speed-up signal delays and to improve electrical properties of the chip. Insertion of buffers and inverters goes alongside with construction of Steiner trees that connect logical sources with possibly many logical sinks and have buffers and inverters as parts of these connections. Classical global routing focuses on packing Steiner trees within the limited routing space. Buffering and global routing have been solved separately in the past. In this thesis we overcome the limitations of the classical approaches by considering the buffering problem as a global, multi-objective problem. We study its theoretical aspects and propose algorithms which we implement in the tool BonnRouteBuffer for timing-constrained global routing with buffered Steiner trees. At its core, we propose a new theoretically founded framework to model timing constraints inherently within global routing. As most important sub-task we have to compute a buffered Steiner tree for a single net minimizing the sum of prices for delays, routing congestion, placement congestion, power consumption, and net length. For this sub-task we present a fully polynomial time approximation scheme to compute an almost-cheapest Steiner tree with a given routing topology and prove that an exact algorithm cannot exist unless P=NP. For topology computation we present a bicriteria approximation algorithm that bounds both the geometric length and the worst slack of the topology. To improve the practical results we present many heuristic modifications, speed-up- and post-optimization techniques for buffered Steiner trees. We conduct experiments on challenging real-world test cases provided by our cooperation partner IBM to demonstrate the quality of our tool. Our new algorithm could produce better solutions with respect to both timing and routability. After post-processing with gate sizing and Vt-assignment, we can even reduce the power consumption on most instances. Overall, our results show that our tool BonnRouteBuffer for timing-constrained global routing is superior to industrial state-of-the-art tools