2,964 research outputs found
Sincronização em sistemas integrados a alta velocidade
Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo
skew) e temporal (baixo jitter ), em sistemas sà ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensÔes dos dispositivos
e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transiçÔes do sinal de relógio tem sido cada vez mais afectada por varia çÔes de processo, tensão e temperatura.
Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sĂ ncrono.
Na prossecu ção deste objectivo principal, esta tese propÔe quatro novos modelos de incerteza com ùmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parùmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitaçÔes temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite
estimar a incerteza em repetidores com liga çÔes RC e assim otimizar o dimensionamento da rede de distribui ção de relĂłgio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruĂ do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom Ănios de sincronismo.
Este modelo pode ser facilmente incorporado numa ferramenta autom atica
para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerĂąncia do sistema ao ru Ădo de alimentação.
Finalmente, usando os modelos propostos, sĂŁo discutidas as tendĂȘncias da precisĂŁo de rel ogio. Conclui-se que os limites da precisĂŁo do rel ogio sĂŁo, em ultima an alise, impostos por fontes de varia ção dinĂąmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo,
esta tese defende a procura de solu çÔes em outros nà veis de abstração, que não apenas o nà vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sà ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically
everywhere (low jitter) in high-performance Integrated Circuits (ICs)
has become an increasingly di cult and time-consuming task, due to technology
scaling. As transistor dimensions shrink and more functionality is
packed into an IC, clock precision becomes increasingly a ected by Process,
Voltage and Temperature (PVT) variations. This thesis addresses the
problem of clock uncertainty in high-performance ICs, in order to determine
the limits of the synchronous design paradigm.
In pursuit of this main goal, this thesis proposes four new uncertainty models,
with di erent underlying principles and scopes. The rst model targets
uncertainty in static CMOS inverters. The main advantage of this model
is that it depends only on parameters that can easily be obtained. Thus,
it can provide information on upcoming constraints very early in the design
stage. The second model addresses uncertainty in repeaters with RC interconnects,
allowing the designer to optimise the repeater's size and spacing,
for a given uncertainty budget, with low computational e ort. The third
model, can be used to predict jitter accumulation in cascaded repeaters, like
clock trees or delay lines. Because it takes into consideration correlations
among variability sources, it can also be useful to promote
oorplan-based
power and clock distribution design in order to minimise jitter accumulation.
A fourth model is proposed to analyse uncertainty in systems with multiple
synchronous domains. It can be easily incorporated in an automatic tool
to determine the best topology for a given application or to evaluate the
system's tolerance to power-supply noise.
Finally, using the proposed models, this thesis discusses clock precision
trends. Results show that limits in clock precision are ultimately imposed
by dynamic uncertainty, which is expected to continue increasing with technology
scaling. Therefore, it advocates the search for solutions at other
abstraction levels, and not only at the physical level, that may increase
system performance with a smaller impact on the assumptions behind the
synchronous design paradigm
Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia
Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-”m CMOS technology and it has a measured peak SNR of 62.5dB
Performances of multi-gap timing RPCs for relativistic ions in the range Z=1-6
We present the performance of Multi-gap timing RPCs under irradiation by
fully stripped relativistic ions (gamma*beta=2.7, Z=1-6). A time resolution of
80 ps at high efficiency has been obtained by just using standard `off the
shelf' 4-gap timing RPCs from the new HADES ToF wall. The resolution worsened
to 100 ps for ~ 1 kHz/cm2 proton flux and for ~ 100 Hz/cm2 Carbon flux. The
chambers were operated at a standard field of E=100 kV/cm and showed a high
stability during the experiment, supporting the fact that RPCs are a convenient
choice when accommodating a very broad range of ionizing particles is needed.
The data provides insight in the region of very highly ionizing particles (up
to x 36 mips) and can be used to constrain the existing avalanche and
Space-Charge models far from the usual `mip valley'. The implications of these
results for the general case of detection based on secondary processes (n,
gamma) resulting in highly ionizing particles with characteristic energy
distributions will be discussed, together with the nature of the time-charge
correlation curve.Comment: 31 pages, 19 figures, submitted to JINS
Enabling Robust State Estimation through Measurement Error Covariance Adaptation
Accurate platform localization is an integral component of most robotic
systems. As these robotic systems become more ubiquitous, it is necessary to
develop robust state estimation algorithms that are able to withstand novel and
non-cooperative environments. When dealing with novel and non-cooperative
environments, little is known a priori about the measurement error uncertainty,
thus, there is a requirement that the uncertainty models of the localization
algorithm be adaptive. Within this paper, we propose the batch covariance
estimation technique, which enables robust state estimation through the
iterative adaptation of the measurement uncertainty model. The adaptation of
the measurement uncertainty model is granted through non-parametric clustering
of the residuals, which enables the characterization of the measurement
uncertainty via a Gaussian mixture model. The provided Gaussian mixture model
can be utilized within any non-linear least squares optimization algorithm by
approximately characterizing each observation with the sufficient statistics of
the assigned cluster (i.e., each observation's uncertainty model is updated
based upon the assignment provided by the non-parametric clustering algorithm).
The proposed algorithm is verified on several GNSS collected data sets, where
it is shown that the proposed technique exhibits some advantages when compared
to other robust estimation techniques when confronted with degraded data
quality.Comment: 14 pages, 13 figures, Submitted to IEEE Transactions on Aerospace And
Electronic System
Design and implementation of a wideband sigma delta ADC
Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTÆ©âM), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications.
The objective of this thesis is to design and implement a wideband CTÆ©âM for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTÆ©âM, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADCâs sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB.
This thesis focuses on the design and implementation of the CTÆ©âM, building upon the principles of a discrete time Æ©â modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTÆ©â modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTÆ©â modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTÆ©âM.
The CTÆ©âMs employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulatorâs performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. TiivistelmĂ€. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistĂ€ tĂ€rkeĂ€mmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnĂ€n kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTÆ©âM), joissa kĂ€ytetÀÀn ylinĂ€ytteistystĂ€ ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun.
TĂ€mĂ€n työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjĂ€rjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTÆ©âM, jolla on 15MHz:n signaalikaistanleveys. YlinĂ€ytteistyssuhde on 25 ja AD muuntimen nĂ€ytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR).
TĂ€mĂ€ työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Æ©â-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmĂ€ esitetÀÀn yksityiskohtaisesti, ja vaatimusten tĂ€yttyminen varmistetaan âtop-downâ -suunnitteluperiaatteella. LiitteenĂ€ on kertoimien laskemiseen kĂ€ytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkĂ€n silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentĂ€ -DA muunninta. Viivekompensointipolkua kĂ€yttĂ€mĂ€llĂ€ modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. LisĂ€ksi FIR takaisinkytkentĂ€ -DA-muuntimen kĂ€yttö pienentÀÀ kellojitteriherkkyyttĂ€, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyĂ€ ja luotettavuutta.
Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty perÀkkÀin integraattoreita myötÀkytkentÀrakenteella (CIFF) ja toisessa sekÀ myötÀ- ettÀ takaisinkytkentÀrakenteella (CIFF-B). PÀÀhuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa kÀyttÀen 0.8 voltin kÀyttöjÀnnitettÀ. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. LisÀksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin
Recommended from our members
Cross-Layer Pathfinding for Off-Chip Interconnects
Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects
- âŠ