A Process Variation Tolerant Self-Compensation Sense Amplifier Design

As we move under the aegis of the Moore\u27s law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Ultra Low Power SubThreshold Device Design Using New Ion Implantation Profile

Title from PDF of title page, viewed August 14, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 92-97)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016One of the important aspects of integrated circuit design is doping profile of a transistor along its length, width and depth. Devices for super-threshold circuit usually employ halo and retrograde doping profiles in the channel to eliminate many unwanted effects like DIBL, short channel effect, threshold variation etc. These effects are always become a serious issue whenever circuit operates at higher supply voltage. Subthreshold circuit operates at lower supply voltage and these kind of effects will not be a serious issue. Since subthreshold circuit will operate at much lower supply voltage then devices for subthreshold circuit does not require halo and retrograde doping profiles. This will reduce the number of steps in the fabrication process, the parasitic capacitance and the substrate noise dramatically. This dissertation introduces four new doping profiles for devices to be used in the ultra low-power subthreshold circuits. The proposed scheme addresses doping variations along all the dimensions (length, width and depth) of the device. Therefore, the approaches are three dimensional (3D) in nature. This new doping scheme proposes to employ Gaussian distribution of doping concentration along the length of the channel with highest concentration at the middle of the channel. The doping concentration across the depth of the device from the channel region towards the bulk of the device can follow one of the following four distributions: (a) exponentially decreasing, (b) Gaussian, (c) low to high, and (d) uniform doping. The proposed doping scheme keeps the doping concentration along the width of the device uniform. Therefore, under this scheme we achieve four sets of new 3D doping profiles. This dissertation also introduces a new comprehensive doping scheme for the transistors in subthreshold circuits. The proposed doping scheme would bring doping changes in the source and drain areas along with the substrate and channel region of the transistors. The proposed doping scheme is characterized by the absence of halos at the source and drain end. We propose a Gaussian doping distribution inside the source, drain region and a low-high-low distribution across the depth of the transistor from the channel surface towards the body region. It also has a low-high-low doping distribution along the length of the transistor below the channel region. Results show that a device optimized with proposed doping profiles would offer higher ON current in the subthreshold region than a device with the conventional halo and retrograde doping profiles. Among the four 3D doping profiles for subthreshold device some has better ON current than others. Based on specific requirements one of these four doping profiles can be adopted for different ultra-low-power applications. Our analysis shows better subthreshold swing can be achieved using new doping profile based subthreshold design. Results also show that the optimized device with the proposed comprehensive doping profile would provide higher ON current (Iₒₙ) at smaller body bias condition. The analysis is performed by changing the doping profile, body bias and (Vgs) to observe the off-state current (Iₒff), threshold voltage variation, magnitude of Iₒₙ/Iₒff ratio, transconductance and the output conductance with the proposed doping profiles.Introduction -- Subthreshold background -- Implantation profiles -- Threshold voltage calculation -- Comprehensive implantation profile -- Conclusion and future workxvi, 98 page

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

ATLAS simulation based characterization of Recessed-S/D FD SOI MOSFETs with non-uniform lateral doping

As scaling down the technology into nanometer regime, short channel effects (SCE) and manufacturing limits will increase, which alters the performance of devices. Silicon-on-insulator (SOI) has got reputation that is a promising technology in the last decade offering more CMOS devices with higher density, higher speed, and reduced second order effects for submicron VLSI applications. Recent investigations have been reported fully depleted (FD) SOI devices are the best solutions because of their suitability to shrinking methods comparative to bulk silicon CMOS devices. Further, implicit the extra advantages, like sub threshold current reduction and improvement in Analog/RF performance; channel engineering and source/drain engineering techniques are implemented in FD SOI MOSFET. Recessed FD SOI MOSFET with non-uniform lateral doping structure gives some solutions to SCEs and better device performance by changing doping levels in different length ratios of channel region in lateral direction In this project work, a comprehensive performance study of source/drain (S/D) engineered SOI MOSFET with non-uniform doping in Channel region is presented. To analyse the characterisation of proposed structure, all the characteristics parameters extracted by using simulation tool. Those characteristics parameters are Surface potential, Threshold voltage, Sub-threshold current, Device capacitances, Drain current, Transconductance, Output conductance, Transconductance generation efficiency, Cut-off frequency and Maximum frequency of oscillation have been carried out and compared with its SOI MOSFETs and non-S/D engineered ones. To extract the characteristics parameters of Device H and Y-parameters are used. All these numerical simulation results are performed using ATLASTM, a 2-D numerical device simulator from SILVACO Inc

Ultra Low Power Digital Circuit Design for Wireless Sensor Network Applications

Ny forskning innenfor feltet trådløse sensornettverk åpner for nye og innovative produkter og løsninger. Biomedisinske anvendelser er blant områdene med størst potensial og det investeres i dag betydelige beløp for å bruke denne teknologien for å gjøre medisinsk diagnostikk mer effektiv samtidig som man åpner for fjerndiagnostikk basert på trådløse sensornoder integrert i et ”helsenett”. Målet er å forbedre tjenestekvalitet og redusere kostnader samtidig som brukerne skal oppleve forbedret livskvalitet som følge av økt trygghet og mulighet for å tilbringe mest mulig tid i eget hjem og unngå unødvendige sykehusbesøk og innleggelser. For å gjøre dette til en realitet er man avhengige av sensorelektronikk som bruker minst mulig energi slik at man oppnår tilstrekkelig batterilevetid selv med veldig små batterier. I sin avhandling ” Ultra Low power Digital Circuit Design for Wireless Sensor Network Applications” har PhD-kandidat Farshad Moradi fokusert på nye løsninger innenfor konstruksjon av energigjerrig digital kretselektronikk. Avhandlingen presenterer nye løsninger både innenfor aritmetiske og kombinatoriske kretser, samtidig som den studerer nye statiske minneelementer (SRAM) og alternative minnearkitekturer. Den ser også på utfordringene som oppstår når silisiumteknologien nedskaleres i takt med mikroprosessorutviklingen og foreslår løsninger som bidrar til å gjøre kretsløsninger mer robuste og skalerbare i forhold til denne utviklingen. De viktigste konklusjonene av arbeidet er at man ved å introdusere nye konstruksjonsteknikker både er i stand til å redusere energiforbruket samtidig som robusthet og teknologiskalerbarhet øker. Forskningen har vært utført i samarbeid med Purdue University og vært finansiert av Norges Forskningsråd gjennom FRINATprosjektet ”Micropower Sensor Interface in Nanometer CMOS Technology”

The Design, Fabrication and Characterization of Independent-Gate FinFETs

The Independent-Gate FinFET is introduced as a novel device structure that combines several innovative aspects of the FinFET and planar double-gate FETs. The IG-FinFET addresses the concerns of scaled CMOS at extremely short channel lengths, by offering the superior short channel control of the double-gate architecture. The IG-FinFET allows for the unique behavioral characteristics of an independent-gate, four-terminal FET. This capability has been demonstrated in planar double-gate architectures, but is intrinsically prohibited by nominal FinFET integration schemes. Finally, the IG-FinFET allows for conventional CMOS manufacturing techniques to be used by leveraging many of the FinFET integration concepts. By introducing relatively few deviations from a standard FinFET fabrication process, the IG-FinFET integration offers the capability of combining three-terminal FinFET devices with four-terminal IG-FinFET devices in one powerful technology for SoC or Analog/RF application, to name only a few. The IG-FinFET device is examined by device modeling, circuit simulation, testsite design, fabrication and electrical characterization. The results of two-dimensional device simulations are presented, and the effects of process variations are discussed in order to understand the desire for a fully self-aligned double-gate architecture. Circuit design is investigated to demonstrate the capabilities of such a double-gate device. Physical designs are also examined, and the layout penalties of implementing such a device are discussed in order to understand the requirement of double-gate and independent-gate integration. A test vehicle is designed and presented for the structural integration and fabrication process development necessary for the demonstration and validation of this novel device architecture. The processing and results of several fabrication experiments are presented, with physical and electrical analysis. The integration changes and process modifications suggested by this analysis are discussed and analyzed. Fabricated devices are then electrically and physically characterized. The final set of fabricated devices show excellent agreement with simulated devices, and experimental verification of double-gate device theory. The results of this work provide for a new and novel device architecture with wide ranging technology application, as well as a new fabrication platform with which to study double-gate device theory and further technology integration

Scaling and intrinsic parameter fluctuations in nanoCMOS devices

The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view