Investigation of switching schemes for three-phase four-leg voltage source inverters

PhD ThesisThree-phase four-leg voltage source inverters (VSIs) are widely used in distributed power generation applications, three-phase UPS systems and fault-mode operation of a balanced three-phase system where the balanced three-phase voltage output is required when the loads are unbalanced. A three-dimensional space vector modulation (3-D SVM) switching scheme, which is proved to be compatible with modern DSP implementation for a four-leg VSI, has the advantage of higher DC link utilization, less harmonic contents and less switching losses compared with sinusoidal PWM. Therefore it is the first choice of switching schemes for a four-leg inverter. Electromagnetic interference (EMI) which is associated with common-mode switching for a high voltage level power system can degrade the equipment performance and cause communication problems. The conventional 3-D SVM switching scheme exhibits high common-mode voltage (CMV) characteristics which may result in problems in high power applications. The 3-D SVM has the drawback of being complex which could become a software burden in computationally intense real-time control applications. Attempts to reduce the complexity of the 3-D SVM have been made by many researchers and new switching schemes such as carrier-based PWM proved to have the same performance. This thesis presents a switching scheme called near-state 3-D SVM that can reduce the CMV voltage level of a four-leg inverter by avoiding the use of the two zero switching states of the inverter. A laboratory test bench has been built to validate the proposed switching scheme. An in-depth analysis has been carried out for a four-leg inverter in terms of total harmonic distortion (THD) factor, current harmonic distortion factor, conduction losses and switching losses. The proposed switching scheme is analyzed and compared with the conventional 3-D SVM using the analysis method. Additionally, a simplified switching scheme which is still based on space vector theory is proposed. This simplified switching scheme remains compatible with vector control. Experimental results show that the simplified switching scheme has the same performance as 3-D SVM, with reduced program execution time. An output voltage control loop with current feed-forward term in d-q-0 coordinate, which is designed in the discrete-time domain, proves to be most compatible with a DSP-based control system. Experimental results demonstrate the performance of the control loop in both steady state and transient operation

A Machine-Independent port of the MPD language run time system to NetBSD

SR (synchronizing resources) is a PASCAL - style language enhanced with constructs for concurrent programming developed at the University of Arizona in the late 1980s. MPD (presented in Gregory Andrews' book about Foundations of Multithreaded, Parallel, and Distributed Programming) is its successor, providing the same language primitives with a different, more C-style, syntax. The run-time system (in theory, identical, but not designed for sharing) of those languages provides the illusion of a multiprocessor machine on a single Unix-like system or a (local area) network of Unix-like machines. Chair V of the Computer Science Department of the University of Bonn is operating a laboratory for a practical course in parallel programming consisting of computing nodes running NetBSD/arm, normally used via PVM, MPI etc. We are considering to offer SR and MPD for this, too. As the original language distributions were only targeted at a few commercial Unix systems, some porting effort is needed. However, some of the porting effort of our earlier SR port should be reusable. The integrated POSIX threads support of NetBSD-2.0 and later allows us to use library primitives provided for NetBSD's phtread system to implement the primitives needed by the SR run-time system, thus implementing 13 target CPUs at once and automatically making use of SMP on VAX, Alpha, PowerPC, Sparc, 32-bit Intel and 64 bit AMD CPUs. We'll present some methods used for the impementation and compare some performance values to the traditional implementation.Comment: 6 page

SOTER: A Runtime Assurance Framework for Programming Safe Robotics Systems

The recent drive towards achieving greater autonomy and intelligence in robotics has led to high levels of complexity. Autonomous robots increasingly depend on third party off-the-shelf components and complex machine-learning techniques. This trend makes it challenging to provide strong design-time certification of correct operation. To address these challenges, we present SOTER, a robotics programming framework with two key components: (1) a programming language for implementing and testing high-level reactive robotics software and (2) an integrated runtime assurance (RTA) system that helps enable the use of uncertified components, while still providing safety guarantees. SOTER provides language primitives to declaratively construct a RTA module consisting of an advanced, high-performance controller (uncertified), a safe, lower-performance controller (certified), and the desired safety specification. The framework provides a formal guarantee that a well-formed RTA module always satisfies the safety specification, without completely sacrificing performance by using higher performance uncertified components whenever safe. SOTER allows the complex robotics software stack to be constructed as a composition of RTA modules, where each uncertified component is protected using a RTA module. To demonstrate the efficacy of our framework, we consider a real-world case-study of building a safe drone surveillance system. Our experiments both in simulation and on actual drones show that the SOTER-enabled RTA ensures the safety of the system, including when untrusted third-party components have bugs or deviate from the desired behavior

The Octopus switch

This chapter1 discusses the interconnection architecture of the Mobile Digital Companion. The approach to build a low-power handheld multimedia computer presented here is to have autonomous, reconfigurable modules such as network, video and audio devices, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules placed in the data streams. Thus, communication between components is not broadcast over a bus but delivered exactly where it is needed, work is carried out where the data passes through, bypassing the memory. The amount of buffering is minimised, and if it is required at all, it is placed right on the data path, where it is needed. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies. The switch is implemented as a simplified ATM switch and provides Quality of Service guarantees and enough bandwidth for multimedia applications. We have built a testbed of the architecture, of which we will present performance and energy consumption characteristics

CAN Fieldbus Communication in the CSP-based CT Library

In closed-loop control systems several realworld entities are simultaneously communicated to through a multitude of spatially distributed sensors and actuators. This intrinsic parallelism and complexity motivates implementing control software in the form of concurrent processes deployed on distributed hardware architectures. A CSP based occam-like architecture seems to be the most convenient for such a purpose. Many, often conflicting, requirements make design and implementation of distributed real-time control systems an extremely difficult task. The scope of this paper is limited to achieving safe and real-time communication over a CAN fieldbus for an\ud existing CSP-based framework