Power and Noise Configurable Phase-Locked Loop Using Multi-Oscillator Feedback Alignment

On-the-fly data rate changes allow for the data rate to be lowered when peak speeds are not needed. A PLL is presented that contains a plurality of sub-VCOs, each able to be enabled or disabled. The goal of this technique is having the power dissipation proportional to the data rate, in order to obtain a fixed energy per transmitted bit. The proposed architecture accomplishes data rate changes by quickly reconfiguring itself and exploiting known power / jitter trade offs in circuit design. The proposed architecture can be applied to either electrical or optical serial links that do not contain a forwarded clock. By relaxing the jitter constraints at lower data rates, the receiver can enter a low-power mode enabling energy savings when maximum data rates are not required. A bank of sub-VCOs is introduced and can be brought up to speed and connected. An activation procedure and compensation methods have also been introduced in order to avoid arbitrary phases during start-up, which would lead to large phase excursions. Simulations show that by enabling the high-performance mode, data rates of 25 Gb/s are able to be obtained in a CDR setting. In the low power mode, the jitter increases by 1.5 times but the power reduces by 46%. In this mode, the architecture can support data rates of 12.5 Gb/s. Therefore, this system responds to the need of improving energy efficiency in receivers by allowing a dynamic reconfiguration of the circuit; varying power in response to jitter specifications

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

The ATLAS TRT electronics

Çetin, Serkant Ali (Dogus Author)The ATLAS inner detector consists of three sub-systems: the pixel detector spanning the radius range 4cm-20cm, the semiconductor tracker at radii from 30 to 52 cm, and the transition radiation tracker (TRT), tracking from 56 to 107 cm. The TRT provides a combination of continuous tracking with many projective measurements based on individual drift tubes (or straws) and of electron identification based on transition radiation from fibres or foils interleaved between the straws themselves. This paper describes the on and off detector electronics for the TRT as well as the TRT portion of the data acquisition (DAQ) system

The ATLAS TRT electronics

The ATLAS inner detector consists of three sub-systems: the pixel detector spanning the radius range 4cm-20cm, the semiconductor tracker at radii from 30 to 52 cm, and the transition radiation tracker (TRT), tracking from 56 to 107 cm. The TRT provides a combination of continuous tracking with many projective measurements based on individual drift tubes (or straws) and of electron identification based on transition radiation from fibres or foils interleaved between the straws themselves. This paper describes the on and off detector electronics for the TRT as well as the TRT portion of the data acquisition (DAQ) system

Elastic circuits

Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.Peer ReviewedPostprint (published version

Online Timing Slack Measurement and its Application in Field-Programmable Gate Arrays

Reliability, power consumption and timing performance are key concerns for today's integrated circuits. Measurement techniques capable of quantifying the timing characteristics of a circuit, while it is operating, facilitate a range of benefits. Delay variation due to environmental and operational conditions, and degradation can be monitored by tracking changes in timing performance. Using the measurements in a closed-loop to control power supply voltage or clock frequency allows for the reduction of timing safety margins, leading to improvements in power consumption or throughput performance through the exploitation of better-than worst-case operation. This thesis describes a novel online timing slack measurement method which can directly measure the timing performance of a circuit, accurately and with minimal overhead. Enhancements allow for the improvement of absolute accuracy and resolution. A compilation flow is reported that can automatically instrument arbitrary circuits on FPGAs with the measurement circuitry. On its own this measurement method is able to track the "health" of an integrated circuit, from commissioning through its lifetime, warning of impending failure or instigating pre-emptive degradation mitigation techniques. The use of the measurement method in a closed-loop dynamic voltage and frequency scaling scheme has been demonstrated, achieving significant improvements in power consumption and throughput performance.Open Acces

On the nature and effect of power distribution noise in CMOS digital integrated circuits

The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,020,000 transistors, of which 510,000 are synchronously active. The circuit is configured as a linear array which, if fabricated using two-micron bulk CMOS technology, would be over eight centimetres long and three millimetres wide. In principle, the array will perform 1.5 x 10 to the power of 11 operations per second. 3. Power distribution noise associated with a non-array-based signal processor which, if fabricated in 2-micron bulk CMOS technology, would occupy 6.7 sq. cm. The circuit contains about 900,000 transistors, of which 600,000 are functional and about 300,000 are used for yield enhancement. The processor uses the RADIX-2 algorithm and is designed to achieve 2 x 10 to the power of 8 floating point operations per second. 4. The extent to which power distribution noise limits the level of integration and/ or performance of such circuits using standard and non-standard fabrication and packaging technology. 5. The extent to which the predicted power distribution noise levels affect circuit susceptibility to transient latch-up and electromigration. It concludes the nature of CMOS digital integrated circuit power distribution noise and recommends ways in which it may be minimised. It outlines an approach aimed at mechanising the developed simulation methodology so that the performance of power distribution networks may more routinely be assessed. Finally. it questions the long term suitability of mainly digital techniques for signal processing

Digital System Design - Use of Microcontroller

Embedded systems are today, widely deployed in just about every piece of machinery from toasters to spacecraft. Embedded system designers face many challenges. They are asked to produce increasingly complex systems using the latest technologies, but these technologies are changing faster than ever. They are asked to produce better quality designs with a shorter time-to-market. They are asked to implement increasingly complex functionality but more importantly to satisfy numerous other constraints. To achieve the current goals of design, the designer must be aware with such design constraints and more importantly, the factors that have a direct effect on them.One of the challenges facing embedded system designers is the selection of the optimum processor for the application in hand; single-purpose, general-purpose or application specific. Microcontrollers are one member of the family of the application specific processors.The book concentrates on the use of microcontroller as the embedded system?s processor, and how to use it in many embedded system applications. The book covers both the hardware and software aspects needed to design using microcontroller.The book is ideal for undergraduate students and also the engineers that are working in the field of digital system design.Contents• Preface;• Process design metrics;• A systems approach to digital system design;• Introduction to microcontrollers and microprocessors;• Instructions and Instruction sets;• Machine language and assembly language;• System memory; Timers, counters and watchdog timer;• Interfacing to local devices / peripherals;• Analogue data and the analogue I/O subsystem;• Multiprocessor communications;• Serial Communications and Network-based interfaces