Scaling and process effect on electromigration reliability for Cu/low k interconnects

textThe microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.Materials Science and Engineerin

Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

Effects of scaling on microstructure evolution of Cu nanolines and impact on electromigration reliability

textScaling can significantly degrade the electromigration (EM) lifetime for Cu interconnects, raising serious reliability concerns. Different methods have emerged to enhance the EM resistance of Cu by suppressing the interface diffusion (the historically fastest diffusion path), notably using CoWP metal cap and Mn alloying. With further scaling of Cu interconnects, EM reliability becomes increasingly complex due to changes in Cu microstructure. In ultra-fine Cu lines a large population of small grains mix with bamboo-type grains, resulting in an additional contribution of grain boundary diffusion to EM degradation. With the interface diffusion suppressed by CoWP or Mn alloying, the grain structure effect becomes even more important. The objective of this study is to investigate the EM reliability of ultra-fine Cu interconnects, focusing on the scaling effect on grain structure and mass transport. First, the detailed microstructure information of Cu interconnects down to the 22 nm node was analyzed using a transmission electron microscope (TEM)-based high resolution diffraction technique. A dominant sidewall growth of {111} grains was observed for 70 nm Cu lines (45 nm node), reflecting the importance of interfacial energy in controlling grain growth. The strength of the {111} texture was found to significantly increase as line width was reduced to 40 nm (22 nm node), while the length fraction of coherent twin boundaries was reduced to ~1%. Secondly, the results from microstructure together with the deduced interfacial and grain boundary diffusivities were used to identify flux divergent sites for void formation and to analyze the grain structure effect on EM statistics using a microstructure-based kinetic model. Finally, based on the analysis of Cu grain structure evolution with downscaling, the scaling behavior of EM drift velocity was investigated for Cu interconnects with CoWP capping and Mn alloying. This enables us to project the EM lifetime and statistics for future technology nodes. The Mn alloying effect on mass transport in combination of grain structure control was found to provide an effective means to improve EM reliability especially with further scaling. In summary, this study establishes a correlation between the microstructure of Cu nanolines, void formation kinetics, and EM statistics.Mechanical Engineerin

Cathode edge displacement by voiding coupled with grain boundary grooving in bamboo like metallic interconnects by surface drift-diffusion under the capillary and electromigration forces

AbstractThe kinetics of cathode edge shrinkage and displacement (drift) coupled strongly with the grain boundary (GB) grooving is investigated using the novel mathematical model developed by Ogurtani, in sandwich type thin film bamboo lines. The computer simulations are performed under the constant current (CC) and the switch-over constant voltage (SOCV) operations. The cathode drift velocity and the cathode failure time show the existence of two distinct phases, depending upon the normalized electron wind intensity parameter χ; the capillary (χ⩽0.01) and the electromigration (EM) dominating regimes (χ>0.01), having current exponent n, equal to 0 and 1, respectively. Analysis of various experimental data on the cathode drift velocity results a consistent value for the surface drift-diffusion coefficient, 1.0×10-5exp(-1.00eV/kT)m2s-1, for copper interconnects exposed to some contaminations during the processing and testing stages. This is found to be an excellent agreement with the experimental values reported in the literature after applying the proper 1/kT correction on the apparent activation enthalpy associated with Nernst–Einstein mobility relationship. The complete cathode failure time (CCFT) due to the cathode area shrinkage by voiding is also formulated by inverse scaling and normalization procedures, which show exactly the same capillary and EM dominating regimes. This formula can be used to predict very accurate CCFT for metallic lines with bamboo-like, near-bamboo, and even with polycrystalline structures by proper calculation of the cathode-edge path length (CEPL) parameter, in terms of the actual line width, the thickness and the grain size

Effects of mechanical properties on the reliability of Cu/low-k metallization systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 211-217).Cu and low-dielectric-constant (k) metallization schemes are critical for improved performance of integrated circuits. However, low elastic moduli, a characteristic of the low-k materials, lead to significant reliability degradation in Cu-interconnects. A thorough understanding of the effects of mechanical properties on electromigration induced failures is required for accurate reliability assessments. During electromigration inside Cu-interconnects, a change in atomic concentration correlates with a change in stress through the effective bulk modulus of the materials system, B, which decreases as the moduli of low-k materials used as inter-level dielectrics (ILDs) decrease. This property is at the core of discussions on electromigration-induced failures by all mechanisms. B is computed using finite element modeling analyses, using experimentally determined mechanical properties of the individual constituents. Characterization techniques include nanoindentation, cantilever deflection, and pressurized membrane deflection for elastic properties measurements, and chevron-notched double-cantilever pull structures for adhesion measurements. The dominant diffusion path in Cu-interconnects is the interface between Cu and the capping layer, which is currently a Si3N4-based film. We performed experiments on Cu-interconnect segments to investigate the kinetics of electromigration. A steady resistance increase over time prior to open-circuit failure, a result of void growth, correlates with the electromigration drift velocity. Diffusive measurements made in this fashion are more fundamental than lifetime measurements alone, and correlate with the combined effects of the electron wind and the back stress forces during electromigration induced void growth.(cont.)Using this method, the electromigration activation energy was determined to be 0.80±0.06eV. We conducted experiments using Cu-interconnects with different lengths to study line length effects. Although a reliability improvement is observed as the segment length decreases, there is no deterministic current-density line-length product, jL, for which all segments are immortal. This is because small, slit-like voids forming directly below vias will cause open-failures in Cu-interconnects. Therefore, the probabilistic jLcrit values obtained from via-above type nterconnects approximate the thresholds for void nucleation. The fact that jLcrit,nuc monotonically decreases with B results from an energy balance between the strain energy released and surface energy cost for void nucleation and the critical stress required for void nucleation is proportional to B. We also performed electromigration experiments using Cu/low-k interconnect trees to investigate the effects of active atomic sinks and reservoirs on interconnect reliability. In all cases, failures were due to void growth. Kinetic parameters were extracted to be ... Quantitative analysis demonstrates that the reliability of the failing segments is modulated by the evolution of stress in the whole interconnect tree. During this process, not only the diffusive parameters but also B play critical roles. However, as B decreases, the positive effects of reservoirs on reliability are diminished, while the negative effects of sinks on reliability are amplified.(cont.) Through comprehensive failure analyses, we also successfully identified the mechanism of electromigration-induced extrusions in Cu/low-k interconnects to be nearmode-I interfacial fracture between the Si3N4-based capping layer and the metallization/ILD layer below. The critical stress required for extrusion is found to depend not only on B but also on the layout and dimensions of the interconnects. As B decreases, sparsely packed, wide interconnects are most prone to extrusion-induced failures. Altogether, this research accounts for the effects of mechanical properties on all mechanisms of failure due to electromigration. The results provide an improved experimental basis for accurate circuit-level, layout-specific reliability assessments.by Frank LiLi Wei.Ph.D

ELECTROMECHANICAL INTERACTION ON THE DEFORMATION BEHAVIOR OF METALLIC MATERIALS

Metallic materials play important roles in providing electrical, thermal, and mechanical functions in electronic devices and systems. The understanding of the electrical-thermal-mechanical interaction caused by the passage of electric current with high density is important to improve the performance and reliability of electronic assembly and packaging. The electromechanical interaction on the deformation behavior of copper and tin is studied in this work. The electromechanical response of Cu strips was studied by passing a DC electric current. The electric resistance linearly increased with time before the occurrence of electric fusing. The electrothermal interaction led to the buckling of the Cu strips with the maximum deflection increasing with the increase of the electric current density. The total strain was found to be proportional to the square of the electric current density. A power law relation was used to describe the dependence of the time-to-fusing on the electric current density. Using the nanoindentation technique, the effect of electric current on the indentation deformation of copper and tin was studied. The reduced contact modulus of copper and tin decreased with increasing the electric current density. With the passage of a DC electric current, the indentation hardness of copper increased slightly with increasing electric current density. With the passage of an AC electric current, the indentation hardness of copper decreased with increasing the indentation deformation. With the passage of a DC electric current, the indentation hardness of tin decreased with increasing the indentation load, showing the normal indentation size effect. Both the limit of infinite depth and the characteristic length were dependent on the electric current density. Using the tensile creep technique, the creep deformation of pure tin was studied with the passage of a DC electric current. The steady state creep rate increased with the increase in temperature, tensile stress and electrical current density. For the same tensile stress and the same chamber temperature, the steady state creep rate increased linearly with the square of the electric current density. The electric current density has no significant effect on the stress exponent and activation energy of the tensile creep of tin for the experimental conditions

Estudo da eletromigração em circuitos integrados na fase de projeto

Orientadores: Roberto Lacerda de Orio, Leandro Tiago ManeraTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O dano por eletromigração nas interconexões é um gargalo bem conhecido dos circuitos integrados, pois causam problemas de confiabilidade. A operação em temperaturas e densidades de corrente elevadas acelera os danos, aumentando a resistência da interconexão e, portanto, reduzindo a vida útil do circuito. Este problema tem se acentuado com o escalonamento da tecnologia. Para garantir a confiabilidade da interconexão e, como consequência, a confiabilidade do circuito integrado, métodos tradicionais baseados no chamado Efeito Blech e numa densidade de corrente máxima permitida são implementados durante o projeto da interconexão. Esses métodos, no entanto, não levam em consideração o impacto da eletromigração no desempenho do circuito. Neste trabalho, a abordagem tradicional é estendida e um método para avaliar o efeito da eletromigração no desempenho de circuito integrado é desenvolvido. O método é implementado em uma ferramenta que identifica as interconexões críticas em um circuito integrado e sugere larguras adequadas com base em diferentes critérios para mitigar os danos à eletromigração e aumentar a confiabilidade. Além disso, é determinada a variação dos parâmetros de desempenho do circuito conforme a resistência das interconexões aumenta. A ferramenta é incorporada ao fluxo de projeto do circuito integrado e usa os dados dos kits de projeto e relatórios diretamente disponíveis no ambiente de projeto. Uma análise precisa da distribuição de temperatura na estrutura de interconexão é essencial para uma melhor avaliação da confiabilidade da interconexão. Portanto, é implementado um modelo para calcular a temperatura em cada nível de metalização da estrutura de interconexão. A distribuição de temperatura nas camadas de metalização de diferentes tecnologias é investigada. É mostrado que a temperatura no Metal 1 da tecnologia Intel 10 nm aumenta 75 K, 12 K mais alta que no Metal 2. Como esperado, as camadas mais próximas dos transistores sofrem um aumento de temperatura mais significativo. A ferramenta é aplicada para avaliar eletromigração nas interconexões e na robustez de diferentes circuitos, como um oscilador em anel, um circuito gerador de tensão de referência tipo bandgap e um amplificador operacional. O amplificador operacional, em particular, é cuidadosamente estudado. A metodologia proposta identifica interconexões críticas que quando danificadas por eletromigração causam grandes variações no desempenho do circuito. No pior cenário, a frequência de corte do circuito varia 65% em 5 anos de operação. Uma descoberta interessante é que a metodologia proposta identifica interconexões críticas que não seriam identificadas pelos critérios tradicionais. Essas interconexões operam com densidades de corrente abaixo do limite recomendado pelas regras de projeto. No entanto, uma dessas interconexões leva a uma variação de 30% no ganho do amplificador operacional. Em resumo, a ferramenta proposta verificou que dos 20% de caminhos com uma densidade crítica de corrente, apenas 3% degradam significativamente o desempenho do circuito. Este trabalho traz o estudo da confiabilidade das interconexões e de circuitos integrados para a fase de projeto, o que permite avaliar a degradação do desempenho do circuito antecipadamente durante o seu desenvolvimento. A ferramenta desenvolvida permite ao projetista identificar interconexões críticas que não seriam detectadas usando o critério de densidade máxima de corrente, levando a uma análise mais ampla e precisa da robustez de circuitos integradosAbstract: Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, because it causes reliability problems. Operation at high temperatures and current densities accelerates the damage, increasing the interconnect resistance and, therefore, reducing the circuit lifetime. This issue has been accentuated with the technology downscaling. To guarantee the interconnect reliability and, as a consequence, the integrated circuit reliability, traditional methods based on the so-called Blech Effect and on the maximum allowed current density are implemented during interconnect design. These methods, however, do not take into account the impact of the electromigration on the circuit performance. In this work the traditional approach is extended and a method to evaluate the effect of the electromigration in an integrated circuit performance is developed. The method is implemented in a tool which identifies the critical interconnect lines of an integrated circuit and suggests the proper interconnect width based on different criteria to mitigate the electromigration damage and to increase the reliability. In addition, the variation of performance parameters of the circuit as an interconnect resistance changes is determined. The tool is incorporated into the design flow of the integrated circuit and uses the data from design kits and reports directly available from the design environment. An accurate analysis of the temperature distribution on the interconnect structure is essential to a better assessment of the interconnect reliability. Therefore, a model to compute the temperature on each metallization level of the interconnect structure is implemented. The temperature distribution on the metallization layers of different technologies is investigated. It is shown that the temperature in the Metal 1 of the Intel 10 nm can increase by 75 K, 12 K higher than in the Metal 2. As expected, the layers that are closer to the transistors undergo a more significant temperature increase. The tool is applied to evaluate the interconnects and the robustness of different circuits, namely a ring oscillator, a bandgap voltage reference circuit, and an operational amplifier, against electromigration. The operational amplifier, in particular, is thoroughly studied. The proposed methodology identifies critical interconnects which under electromigration cause large variations in the performance of the circuit. In a worst-case scenario, the cutoff frequency of the circuit varies by 65% in 5 years of operation. An interesting finding is that the proposed methodology identifies critical interconnects which would not be identified by the traditional criteria. These interconnects have current densities below the limit recommended by the design rules. Nevertheless, one of such an interconnect leads to a variation of 30% in the gain of the operational amplifier. In summary, the proposed tool verified that from the 20% paths with a critical current density, only 3% degrades significantly the circuit performance. This work brings the study of the reliability of the interconnects and of integrated circuits to the design phase, which provides the assessment of a circuit performance degradation at an early stage of development. The developed tool allows the designer to identify critical interconnects which would not be detected using the maximum current density criterion, leading to more accurate analysis of the robustness of integrated circuitsDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétrica88882.329437/2019-01CAPE

Interconnect Aging—Physics to Software

Device reliability or lifetime is often non-negotiable and crucial for sensitive applications such as medical devices, autonomous vehicles and space crafts. Inevitable technology advancement (e.g. miniaturization) has added unwelcome complications and unpredictability to the aging problem. Reliability of VLSI chips is jeopardized by mass transport in metallic interconnects. Material migration is caused by electrical, mechanical and thermal phenomena, and, therefore, is a complicated process. While all aspects of material migration have been studied, a comprehensive investigation that can explain and include all those phenomena simultaneously remains unsolved. Inaccuracies in modeling and predicting aging processes in wires cause that chipmakers often overdesign interconnects. This is an undesirable and expensive approach in terms of time and cost. In modern technologies, the predicted lifetime, aging, and failure mechanisms in interconnect very often do not match the observed behaviors. Unrealistic models used in CAD tools are the main culprit of such incompatibilities. In general, two situations may occur: (1) in some cases, the models may wrongly scrutinize reliability in unfailing parts and consequently impose unnecessary design tightening and (2) in some other cases, the models may underestimate serious reliability problems causing unpredicted behaviors or catastrophic failures to occur. The existing models for reliability evaluation are usually pessimistic in case of interconnect voiding and optimistic when extrusions occur. Time-consuming and not converging reliability assessments, as well as undesired chip behaviors, are the common expensive outcome of such models.We revisit the underlying physics of aging processes in dual-damascene copper lines. We demonstrate, that the simplistic modeling is the cause of the incompatibility of the existing models. We study all three main aging processes: electromigration, thermo-migration, and stress migration and offer several comprehensive yet compact models for realistic assessment of interconnect aging. These models explain many observations that have been inexplicable for decades. Ultimately, a computer-aided design tool, RAIN, is developed based on the proposed models and is capable of assessing the reliability of industry standard complex multi-layer, multi-segment interconnect networks. This tool can be readily integrated into other verification signoffs phases such as performance, timing, and power analyses. RAIN takes as inputs: (1) interconnect design, (2) technology specifications, (3) initial stress and temperature, (4) IR drop and lifetime requirements. It analyzes and assesses reliability and delivery requirements of all nets, and provides a report on voltage limitations, thermal violations and expected lifetime. It is validated on a wide spectrum of experimental results performed on various industry benchmarks

Tunable Copper Microstructures in Blanket Films and Trenches Using Pulsed Electrodeposition

Copper interconnects in microelectronics have long been plagued with thermo-mechanical reliability issues. Control over the copper deposition process and resulting microstructure can dictate its material properties and reduce stresses as well as defects that form in the copper. In this thesis, pulse electrodeposition processing parameters were evaluated for their impact on the copper microstructure (grain size, texture, and twin density and stress state) through electron backscattering diffraction and wafer curvature measurements. Varying levels of constraint were also investigated for their effect on the copper microstructure to better understand the microstructures of more complex three-dimensional interconnects. Highly texture blanket copper films were deposited with various pulse frequencies and duty cycle, which was found to control grain size, orientation, and twin density. Higher twin densities were also observed in the films with lower residual stress. The findings from blanket film studies were carried over to trench deposited samples, where the influence of organic additives, typically used in the electrolytic bath to produce defect-free filling of advanced geometries, on the copper microstructure was studied. With the addition of organic additives, depositions produced finer grained structures with an increased contribution from the microstructure of the trench sidewall seed layer, especially with increasing trench aspect ratio. In addition, the increased constraint of the copper, resulted in larger stresses within the features and higher twin densities. The core of this dissertation demonstrated the ability to alter the resulting Cu microstructure through variations in pulse electrodeposition parameters