A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation

Low-Power Wake-Up Receivers

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Integrated realizations of reconfigurable low pass and band pass filters for wide band multi-mode receivers

With the explosive development of wireless communication systems the specifications of the supporting hardware platforms have become more and more demanding. According to the long term goals of the industry, future communications systems should integrate a wide variety of standards. This leads to the idea of software defined radio, implemented on fully reconfigurable hardware.Among other reconfigurable hardware blocks, suitable for the software radio concept, an outstanding importance belongs to the reconfigurable filters that are responsible for the selectivity of the system. The problematic of filtering is strictly connected to the architecture chosen for a multi-mode receiver realization. According to the chosen architecture, the filters can exhibit low pass or band pass frequency responses.The idea of reconfigurable frequency parameters has been introduced since the beginning of modern filtering applications due to the required precision of the frequency response. However, the reconfiguration of the parameters was usually done in a limited range around ideal values. The purpose of the presented research is to transform the classical filter structures with simple self-correction into fully reconfigurable filters over a wide range of frequencies. The ideal variation of the frequency parameters is continuous and consequently difficult to implement in real circuits. Therefore, it is usually sufficient to use a discrete programming template with reasonably small steps.There are several methods to implement variable frequency parameters. The most often used programming templates employ resistor and capacitor arrays, switched according to a given code. The low pass filter implementation proposed in this work uses a special switching template, optimized for a quasi-linear frequency variation over logarithmic axes. The template also includes the possibility to compensate errors caused by component tolerances and temperature. Another important topic concerns the implementation of programmable band pass filters, suitable for IF sampling receivers. The discussion is centered on the feasibility and the flexibility of different band pass filter architectures. Due to the high frequency requirements, the emphasis lays on filters that employ transconductance amplifiers and capacitors.Die rasch fortschreitende Entwicklung drahtloser Kommunikationssysteme führt zu immer anspruchsvolleren Spezifikationen der diese Systeme unterstützenden Hardwareplattformen. Zukünftige Kommunikationssysteme sollen übereinstimmend mit den längerfristigen Zielen der Industrie verschiedene Standards integrieren. Dies führt zu der Idee von vollständig rekonfigurierbarer Hardware, welche mittels Software gesteuert wird.Inmitten anderer rekonfigurierbarer Hardwareblöcke, die für das Software Radio Konzept geeignet sind, besitzen die steuerbaren Filter, welche wesentlichen Einfluss auf die Selektivität des Systems haben, eine enorme Bedeutung. Die Filterproblematik ist eng mit der gewählten Architektur der standardübergreifenden Empfängerrealisierung verknüpft. Die Filter können entsprechend der ausgesuchten Architektur Tiefpass- oder Bandpasscharakter annehmen.Die Idee rekonfigurierbarer Frequenzparameter wurde bereits mit Beginn moderner Filteranwendungen auf Grund geforderter Frequenzganggenauigkeit umgesetzt. Jedoch wurde die Parameterrekonfiguration üblicherweise nur in einem begrenzten Bereich um die Idealwerte herum vorgenommen. Das Ziel der vorgestellten Forschungsarbeit ist es, diese klassischen Filterstrukturen mit einfacher Selbstkorrektur in über große Frequenzbereiche voll rekonfigurierbare Filter zu transformieren. Idealerweise werden die Frequenzparameter kontinuierlich variiert weswegen sich die Implementierung in reellen Schaltkreisen als schwierig erweist. Deshalb ist es üblicherweise ausreichend, ein diskretes Steuerschema mit kleinen Schrittweiten zu verwenden.Es gibt verschiedene Methoden, variable Frequenzparameter zu implementieren. Die meisten Schemata verwenden Widerstands- und Kondensatorfelder, die entsprechend eines Kodes geschaltet werden. Die in dieser Arbeit vorgestellte Implementierung eines Tiefpassfilters nutzt ein spezielles Umschaltschema, welches für die quasi-lineare Frequenzvariation bei Darstellung über logarithmischen Axen optimiert wurde. Es beinhaltet weiterhin die Möglichkeit, Fehler zu kompensieren, die durch Bauelementtoleranzen und Temperaturschwankungen hervorgerufen werden.Ein weiteres interessantes Thema betrifft die Implementierung steuerbarer Bandpassfilter, die für Empfänger mit Zwischenfrequenzabtastung geeignet sind. Die Betrachtung beschränkt sich hierbei auf die Durchführbarkeit und Flexibilität verschiedener Bandpassfilterarchitekturen. Auf Grund hoher Frequenzanforderungen liegt der Schwerpunkt auf Filtern, die auf Transkonduktanzverstärkern und Kondensatoren basieren

Bluetooth/WLAN receiver design methodology and IC implementations

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

Low-noise amplifiers for integrated multi-mode direct-conversion receivers

The evolution of wireless telecommunication systems during the last decade has been rapid. During this time the design driver has shifted towards fast data applications instead of speech. In addition, the different systems may have a limited coverage, for example, limited to urban areas only. Thus, it has become important for a mobile terminal to be able to use different wireless systems, depending on the application chosen and the location of the terminal. The choice of receiver architecture affects the performance, size, and cost of the receiver. The superheterodyne receiver has hitherto been the dominant radio architecture, because of its good sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which, with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore, architectures using a minimum number of external components, such as direct conversion, have become popular. In addition, compared to the superheterodyne architecture, the direct-conversion architecture has benefits when multi-mode receivers, which are described in this thesis, are being designed. In this thesis, the limitations placed on the analog receiver by different system specifications are introduced. The estimations for the LNA specifications are derived from these specifications. In addition, the limitations imposed by different types of receiver architectures are described. The inductively-degenerated LNA is the basis for all the experimental circuits. The different components for this configuration are analyzed and compared to other commonly-used configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed. Without knowing these limitations, it becomes difficult to understand the choices made in the experimental circuits. One of the key parts of this thesis describes the design and implementation of a single-chip multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode structures in this thesis were developed for a direct-conversion receiver where only one system is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different LNA components are analyzed in detail. Furthermore, the design issues related to possible interference from additional systems on single-chip receivers are analyzed and demonstrated. A typical receiver includes variable gain, which can be implemented both in the analog baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically placed in the LNA or in a separate gain control stage. Several methods that can be used to implement a variable gain in the LNA are introduced and compared to each other. Furthermore, several of these methods are included in the experimental circuits. The last part of this thesis concentrates on four experimental circuits, which are described in this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D converters on the same chip as sensitive RF blocks without significantly degrading receiver performance. The other two chips describe an RF front-end for WCDMA and GSM900 applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA systems. These ICs demonstrate the usability of the circuit structure developed and presented in this thesis. The chip area in the last multi-mode receiver is not significantly increased compared to corresponding single-system receivers.reviewe

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system

Fully-Integrated Magnetic-Free Nonreciprocal Components by Breaking Lorentz Reciprocity: from Physics to Applications

Reciprocity is a fundamental physical precept that governs wave propagation in a wide variety of physical domains. The various reciprocity theorems state that the response of a system remains unchanged if the excitation source and the measuring point are interchanged within a medium, and are closely related to the concept of time reversal symmetry in physics. Lorentz reciprocity is a fundamental characteristic of linear, time-invariant electronic and photonic structures with symmetric permittivity and permeability tensors. However, breaking reciprocity enables the realization of nonreciprocal components, such as isolators and circulators, which are critical to electronic, optical and acoustic systems, as well as new functionalities and devices based on novel wave propagation modes. Nonreciprocal components have traditionally relied on magnetic materials such as ferrites that lose reciprocity under the application of an external magnetic field through the Faraday Effect. The need for a magnetic bias limits the applicability of such approaches in small-form-factor Complementary Metal–Oxide–Semiconductor (CMOS)-compatible integrated devices. One of the main features of CMOS technology is the availability of high-speed transistor switches which can be turned ON and OFF, modulating the conductance of the medium. In this dissertation, a novel approach to break Lorentz reciprocity is presented based on staggered commutation in Linear Periodically-Time-Varying (LPTV) circuits. We have demonstrated the world’s first CMOS passive magnetic-free nonreciprocal circulator through spatio-temporal conductivity modulation. Since conductivity in semiconductors can be modulated over a wide range (CMOS transistor ON/OFF conductance ratio at Radio Frequency (RF)/millimeter-wave frequencies is as high as 103-105), commutated LPTV networks break reciprocity within a deeply sub-wavelength form-factor with low loss and high linearity. The resulting nonreciprocal components find application in antenna interfaces of wireless communication systems, connecting the Transmitter (TX) and the Receiver (RX) to a shared antenna. This is particularly important for full-duplex wireless, where the TX and the RX operate simultaneously at the same frequency band and need to be highly isolated in order to maintain receiver sensitivity. Multiple fully-integrated full-duplex receivers are demonstrated in this dissertation that best show the synergy between the physical concept and application-based implementations by using circuit techniques to benefit the system-level performance, such as TX-side linearity enhancement and co-design and co-optimization of the antenna interface and the RX and utilization of the multi-phase structure of our antenna interfaces for analog beamforming in multi-antenna systems. Finally, this dissertation discusses some of the fundamental limits of space-time modulated nonreciprocal structures, as well as new directions to build nonreciprocal components which can ideally be infinitesimal in size. A novel family of inductor-less nonreciprocal components including circulators and isolators have been demonstrated that achieve a wide tuning range in an infinitesimal form-factor. This family of devices combine reciprocal and nonreciprocal modes of operation, through the transfer properties of fundamental and harmonics of the system and enable a wide variety of functionalities