9,406 research outputs found
Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology
A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging
This report reviews current trends in the R&D of semiconductor pixellated
sensors for vertex tracking and radiation imaging. It identifies requirements
of future HEP experiments at colliders, needed technological breakthroughs and
highlights the relation to radiation detection and imaging applications in
other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory
Grou
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Directed Placement for mVLSI Devices
Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural "directedness" in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies
Integration techniques of pHEMTs and planar Gunn diodes on GaAs substrates
This work presents two different approaches for the implementation of pseudomorphic high electron mobility transistors (pHEMTs) and planar Gunn diodes on the same gallium arsenide substrate. In the first approach, a combined wafer is used where a buffer layer separates the active layers of the two devices. A second approach was also examined using a single wafer where the AlGaAs/InGaAs/GaAs heterostructures were designed for the realisation of pHEMTs. The comparison between the two techniques showed that the devices fabricated on the single pHEMT wafer presented superior performance over the combined wafer technique. The DC and small-signal characteristics of the pHEMTs on the single wafer were enhanced after the use of T-gates with 70 nm length. The maximum transconductance of the transistors was equal to 780 mS/mm with 200 GHz maximum frequency of oscillation (fmax). Planar Gunn diodes fabricated in the pHEMT wafer, with 1.3 μm anode-to-cathode separation (LAC) presented oscillations at 87.6 GHz with maximum power of oscillation equal to -40 dBm
Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.
Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them
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Monolithic ultrasound fingerprint sensor.
This paper presents a 591×438-DPI ultrasonic fingerprint sensor. The sensor is based on a piezoelectric micromachined ultrasonic transducer (PMUT) array that is bonded at wafer-level to complementary metal oxide semiconductor (CMOS) signal processing electronics to produce a pulse-echo ultrasonic imager on a chip. To meet the 500-DPI standard for consumer fingerprint sensors, the PMUT pitch was reduced by approximately a factor of two relative to an earlier design. We conducted a systematic design study of the individual PMUT and array to achieve this scaling while maintaining a high fill-factor. The resulting 110×56-PMUT array, composed of 30×43-μm2 rectangular PMUTs, achieved a 51.7% fill-factor, three times greater than that of the previous design. Together with the custom CMOS ASIC, the sensor achieves 2 mV kPa-1 sensitivity, 15 kPa pressure output, 75 μm lateral resolution, and 150 μm axial resolution in a 4.6 mm×3.2 mm image. To the best of our knowledge, we have demonstrated the first MEMS ultrasonic fingerprint sensor capable of imaging epidermis and sub-surface layer fingerprints
Trends in Pixel Detectors: Tracking and Imaging
For large scale applications, hybrid pixel detectors, in which sensor and
read-out IC are separate entities, constitute the state of the art in pixel
detector technology to date. They have been developed and start to be used as
tracking detectors and also imaging devices in radiography, autoradiography,
protein crystallography and in X-ray astronomy. A number of trends and
possibilities for future applications in these fields with improved
performance, less material, high read-out speed, large radiation tolerance, and
potential off-the-shelf availability have appeared and are momentarily matured.
Among them are monolithic or semi-monolithic approaches which do not require
complicated hybridization but come as single sensor/IC entities. Most of these
are presently still in the development phase waiting to be used as detectors in
experiments. The present state in pixel detector development including hybrid
and (semi-)monolithic pixel techniques and their suitability for particle
detection and for imaging, is reviewed.Comment: 10 pages, 15 figures, Invited Review given at IEEE2003, Portland,
Oct, 200
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