A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N phase-locked loop (FN-PLL) and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed fractional-N sampling phase-locked loop (FN-SPLL)

Timing Signals and Radio Frequency Distribution Using Ethernet Networks for High Energy Physics Applications

Timing networks are used around the world in various applications from telecommunications systems to industrial processes, and from radio astronomy to high energy physics. Most timing networks are implemented using proprietary technologies at high operation and maintenance costs. This thesis presents a novel timing network capable of distributed timing with subnanosecond accuracy. The network, developed at CERN and codenamed “White- Rabbit”, uses a non-dedicated Ethernet link to distribute timing and data packets without infringing the sub-nanosecond timing accuracy required for high energy physics applications. The first part of this thesis proposes a new digital circuit capable of measuring time differences between two digital clock signals with sub-picosecond time resolution. The proposed digital circuit measures and compensates for the phase variations between the transmitted and received network clocks required to achieve the sub-nanosecond timing accuracy. Circuit design, implementation and performance verification are reported. The second part of this thesis investigates and proposes a new method to distribute radio frequency (RF) signals over Ethernet networks. The main goal of existing distributed RF schemes, such as Radio-Over-Fibre or Digitised Radio-Over-Fibre, is to increase the bandwidth capacity taking advantage of the higher performance of digital optical links. These schemes tend to employ dedicated and costly technologies, deemed unnecessary for applications with lower bandwidth requirements. This work proposes the distribution of RF signals over the “White-Rabbit” network, to convey phase and frequency information from a reference base node to a large numbers of remote nodes, thus achieving high performance and cost reduction of the timing network. Hence, this thesis reports the design and implementation of a new distributed RF system architecture; analysed and tested using a purpose-built simulation environment, with results used to optimise a new bespoke FPGA implementation. The performance is evaluated through phase-noise spectra, the Allan-Variance, and signalto- noise ratio measurements of the distributed signals

The Development of a High Performance Digital RF Transmitter for NMR

This Master’s thesis consists of the development of a Nuclear Magnetic Resonance (NMR) Radio Frequency (RF) transmitter, which is a core electronic subsystem of an NMR system. The main purpose of this research is to contribute to the application of NMR, which is a new sensing technology that has yet to be fully implemented into the everyday world. One of the barriers to adopting this technology is its complexity. However, the invention of high speed digital FPGAs (Field Programmable Gate Array) such as the Spartan series has made it easier to develop high performance NMR systems over recent years. The major contribution to this research is the development of faster digital signal processing hardware, and methodologies that have been implemented on a single chip. This has reduced the size and the cost of the electronic subsystem and contributed towards the evolution of NMR as a general tool. This thesis introduces the concept of implementing a high-speed NMR RF multi-frequency transmitter by using multiple Direct Digital Synthesis (DDS) cores to generate sine-waves, which range from 100 kHz to 750 MHz. The research required three stages to be achieved, beginning with conceptual design of a high-speed transmitter using MATLAB-Simulink, RTL-level (Register-Transfer Level) simulation and hardware implementation, which included hardware testing on a prototype board. This Master’s research is to seek a solution to building a multi-core DDS module in an FPGA device. In other words, the research work focuses on finding an alternative solution to constructing a DDS system. The project involves building up the VHSIC Hardware Description Language (VHDL) program to work beyond the hardware limitation of an FPGA device. Hence, the final solution does not consider any noise impact due to the structure of the developed system

The optimal control of power electronic embedded networks in More Electric Aircraft

With the advancement of power electronic technologies over recent decades, there has been an overall increase in the utilisation of distributed generation and power electronic embedded networks in a large sphere of applications. Probably one of the most prominent areas of utilisation of new power electronics embedded systems is the use in power networks onboard military and civilian aircraft. With environmental concerns and increased competition in the civil aviation sector, more aircraft manufactures are replacing and interfacing electrical alternatives over heavier, less efficient and costly pneumatic, hydraulic and mechanical systems. In these modern power systems, the increased proliferation of power electronic converters and distributed generation raises important issues in regards to the performance, stability and robustness between interfaced switching units. These phenomena, such as power electronic sub-system interactions, become even more prominent in micro-grid applications or other low voltage distribution systems where interfaced converters are in close proximity to one another. In More Electric Aircraft (MEA), these interfaced power electronic converters are connected to the same non-stiff low power AC grid, which further increases the interactive effects between converter sub-systems. If these effects are not properly taken into account, then external disturbances to the system at given operating conditions can result in degradation of the system performance, failure in meeting the operating requirements of the grid, or in the worst case, instability of the whole grid. With much research in the area of decreasing the size and weight of systems, there is much literature proposing optimisation methods which decrease the size of filters between interfacing converters. Whilst effectively decreasing the size of these systems, interactions between interfaced converters gets worse, and is often improperly accounted for. The work presented in this thesis proposes a novel approach to the decentralisation and optimisation of converter controls on a power electronics embedded power network. In order to account for the interactive dynamics between sub-systems in the environment of reduced passive filter networks, all the system dynamics including the interactive terms are modelled globally. An optimal controller design approach based on the H2 optimisation is proposed to synthesise and generate automatically the controller gains for each power electronic sub-system. H2 optimisation is a powerful tool, which not only allows the submission, optimisation and development of closed loop controls for large dynamic systems, but offers the ability to the user to construct the controller for given structures. This enables the development of decentralised controllers for every sub-system with intrinsic knowledge of the closed loop dynamics of every other interconnect sub-system. It is shown through simulation and by experimental validation that this novel approach to grid control optimisation not only can improve overall dynamic performance of all sub-systems over 15traditional methods of design, but can also intrinsically reduce or better yet mitigate against the interactive effects between all converters. In addition, this method of controller design will be shown to not only be scalable to expanding sizes of grids, but the Phase-locked loops (PLLs) integrated to grid connected devices can also be considered in the optimisation procedure. PLLs are widely known to further cause interactive behaviours between grid interfaced devices. Including this into the optimisation also has been validated experimentally to prevent interactions on the grid, and improve performance over traditional design methods. Adaptations to the controller are performed to ensure operation in variable frequency environments (as is common in MEA), as well as methods of single converter optimisation when interfacing to an unknown grid. Additionally some initial research towards an adaption of the H2 controller to incorporate robustness as well as performance into the optimisation procedure is presented with mathematical concepts shown through simulation

Development of a Full-Field Time-of-Flight Range Imaging System

A full-field, time-of-flight, image ranging system or 3D camera has been developed from a proof-of-principle to a working prototype stage, capable of determining the intensity and range for every pixel in a scene. The system can be adapted to the requirements of various applications, producing high precision range measurements with sub-millimetre resolution, or high speed measurements at video frame rates. Parallel data acquisition at each pixel provides high spatial resolution independent of the operating speed. The range imaging system uses a heterodyne technique to indirectly measure time of flight. Laser diodes with highly diverging beams are intensity modulated at radio frequencies and used to illuminate the scene. Reflected light is focused on to an image intensifier used as a high speed optical shutter, which is modulated at a slightly different frequency to that of the laser source. The output from the shutter is a low frequency beat signal, which is sampled by a digital video camera. Optical propagation delay is encoded into the phase of the beat signal, hence from a captured time variant intensity sequence, the beat signal phase can be measured to determine range for every pixel in the scene. A direct digital synthesiser (DDS) is designed and constructed, capable of generating up to three outputs at frequencies beyond 100 MHz with the relative frequency stability in excess of nine orders of magnitude required to control the laser and shutter modulation. Driver circuits were also designed to modulate the image intensifier photocathode at 50 Vpp, and four laser diodes with a combined power output of 320 mW, both over a frequency range of 10-100 MHz. The DDS, laser, and image intensifier response are characterised. A unique method of measuring the image intensifier optical modulation response is developed, requiring the construction of a pico-second pulsed laser source. This characterisation revealed deficiencies in the measured responses, which were mitigated through hardware modifications where possible. The effects of remaining imperfections, such as modulation waveform harmonics and image intensifier irising, can be calibrated and removed from the range measurements during software processing using the characterisation data. Finally, a digital method of generating the high frequency modulation signals using a FPGA to replace the analogue DDS is developed, providing a highly integrated solution, reducing the complexity, and enhancing flexibility. In addition, a novel modulation coding technique is developed to remove the undesirable influence of waveform harmonics from the range measurement without extending the acquisition time. When combined with a proposed modification to the laser illumination source, the digital system can enhance range measurement precision and linearity. From this work, a flexible full-field image ranging system is successfully realised. The system is demonstrated operating in a high precision mode with sub-millimetre depth resolution, and also in a high speed mode operating at video update rates (25 fps), in both cases providing high (512 512) spatial resolution over distances of several metres

The optimal control of power electronic embedded networks in More Electric Aircraft

With the advancement of power electronic technologies over recent decades, there has been an overall increase in the utilisation of distributed generation and power electronic embedded networks in a large sphere of applications. Probably one of the most prominent areas of utilisation of new power electronics embedded systems is the use in power networks onboard military and civilian aircraft. With environmental concerns and increased competition in the civil aviation sector, more aircraft manufactures are replacing and interfacing electrical alternatives over heavier, less efficient and costly pneumatic, hydraulic and mechanical systems. In these modern power systems, the increased proliferation of power electronic converters and distributed generation raises important issues in regards to the performance, stability and robustness between interfaced switching units. These phenomena, such as power electronic sub-system interactions, become even more prominent in micro-grid applications or other low voltage distribution systems where interfaced converters are in close proximity to one another. In More Electric Aircraft (MEA), these interfaced power electronic converters are connected to the same non-stiff low power AC grid, which further increases the interactive effects between converter sub-systems. If these effects are not properly taken into account, then external disturbances to the system at given operating conditions can result in degradation of the system performance, failure in meeting the operating requirements of the grid, or in the worst case, instability of the whole grid. With much research in the area of decreasing the size and weight of systems, there is much literature proposing optimisation methods which decrease the size of filters between interfacing converters. Whilst effectively decreasing the size of these systems, interactions between interfaced converters gets worse, and is often improperly accounted for. The work presented in this thesis proposes a novel approach to the decentralisation and optimisation of converter controls on a power electronics embedded power network. In order to account for the interactive dynamics between sub-systems in the environment of reduced passive filter networks, all the system dynamics including the interactive terms are modelled globally. An optimal controller design approach based on the H2 optimisation is proposed to synthesise and generate automatically the controller gains for each power electronic sub-system. H2 optimisation is a powerful tool, which not only allows the submission, optimisation and development of closed loop controls for large dynamic systems, but offers the ability to the user to construct the controller for given structures. This enables the development of decentralised controllers for every sub-system with intrinsic knowledge of the closed loop dynamics of every other interconnect sub-system. It is shown through simulation and by experimental validation that this novel approach to grid control optimisation not only can improve overall dynamic performance of all sub-systems over 15traditional methods of design, but can also intrinsically reduce or better yet mitigate against the interactive effects between all converters. In addition, this method of controller design will be shown to not only be scalable to expanding sizes of grids, but the Phase-locked loops (PLLs) integrated to grid connected devices can also be considered in the optimisation procedure. PLLs are widely known to further cause interactive behaviours between grid interfaced devices. Including this into the optimisation also has been validated experimentally to prevent interactions on the grid, and improve performance over traditional design methods. Adaptations to the controller are performed to ensure operation in variable frequency environments (as is common in MEA), as well as methods of single converter optimisation when interfacing to an unknown grid. Additionally some initial research towards an adaption of the H2 controller to incorporate robustness as well as performance into the optimisation procedure is presented with mathematical concepts shown through simulation

A novel parallel algorithm for surface editing and its FPGA implementation

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophySurface modelling and editing is one of important subjects in computer graphics. Decades of research in computer graphics has been carried out on both low-level, hardware-related algorithms and high-level, abstract software. Success of computer graphics has been seen in many application areas, such as multimedia, visualisation, virtual reality and the Internet. However, the hardware realisation of OpenGL architecture based on FPGA (field programmable gate array) is beyond the scope of most of computer graphics researches. It is an uncultivated research area where the OpenGL pipeline, from hardware through the whole embedded system (ES) up to applications, is implemented in an FPGA chip. This research proposes a hybrid approach to investigating both software and hardware methods. It aims at bridging the gap between methods of software and hardware, and enhancing the overall performance for computer graphics. It consists of four parts, the construction of an FPGA-based ES, Mesa-OpenGL implementation for FPGA-based ESs, parallel processing, and a novel algorithm for surface modelling and editing. The FPGA-based ES is built up. In addition to the Nios II soft processor and DDR SDRAM memory, it consists of the LCD display device, frame buffers, video pipeline, and algorithm-specified module to support the graphics processing. Since there is no implementation of OpenGL ES available for FPGA-based ESs, a specific OpenGL implementation based on Mesa is carried out. Because of the limited FPGA resources, the implementation adopts the fixed-point arithmetic, which can offer faster computing and lower storage than the floating point arithmetic, and the accuracy satisfying the needs of 3D rendering. Moreover, the implementation includes Bézier-spline curve and surface algorithms to support surface modelling and editing. The pipelined parallelism and co-processors are used to accelerate graphics processing in this research. These two parallelism methods extend the traditional computation parallelism in fine-grained parallel tasks in the FPGA-base ESs. The novel algorithm for surface modelling and editing, called Progressive and Mixing Algorithm (PAMA), is proposed and implemented on FPGA-based ES’s. Compared with two main surface editing methods, subdivision and deformation, the PAMA can eliminate the large storage requirement and computing cost of intermediated processes. With four independent shape parameters, the PAMA can be used to model and edit freely the shape of an open or closed surface that keeps globally the zero-order geometric continuity. The PAMA can be applied independently not only FPGA-based ESs but also other platforms. With the parallel processing, small size, and low costs of computing, storage and power, the FPGA-based ES provides an effective hybrid solution to surface modelling and editing

SpiNNaker - A Spiking Neural Network Architecture

20 years in conception and 15 in construction, the SpiNNaker project has delivered the world’s largest neuromorphic computing platform incorporating over a million ARM mobile phone processors and capable of modelling spiking neural networks of the scale of a mouse brain in biological real time. This machine, hosted at the University of Manchester in the UK, is freely available under the auspices of the EU Flagship Human Brain Project. This book tells the story of the origins of the machine, its development and its deployment, and the immense software development effort that has gone into making it openly available and accessible to researchers and students the world over. It also presents exemplar applications from ‘Talk’, a SpiNNaker-controlled robotic exhibit at the Manchester Art Gallery as part of ‘The Imitation Game’, a set of works commissioned in 2016 in honour of Alan Turing, through to a way to solve hard computing problems using stochastic neural networks. The book concludes with a look to the future, and the SpiNNaker-2 machine which is yet to come

SpiNNaker - A Spiking Neural Network Architecture

20 years in conception and 15 in construction, the SpiNNaker project has delivered the world’s largest neuromorphic computing platform incorporating over a million ARM mobile phone processors and capable of modelling spiking neural networks of the scale of a mouse brain in biological real time. This machine, hosted at the University of Manchester in the UK, is freely available under the auspices of the EU Flagship Human Brain Project. This book tells the story of the origins of the machine, its development and its deployment, and the immense software development effort that has gone into making it openly available and accessible to researchers and students the world over. It also presents exemplar applications from ‘Talk’, a SpiNNaker-controlled robotic exhibit at the Manchester Art Gallery as part of ‘The Imitation Game’, a set of works commissioned in 2016 in honour of Alan Turing, through to a way to solve hard computing problems using stochastic neural networks. The book concludes with a look to the future, and the SpiNNaker-2 machine which is yet to come