849 research outputs found

    A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

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    This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.This work has been supported, within the fund for research groups of the Basque university system IT1440-22, by the Department of Education and, within PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects, by the Hazitek program, both of the Basque Government; the latter also by the Ministerio de Ciencia Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the projects IDI-20201264 and IDI-20220543, and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)

    Design and characterisation of monolithic CMOS detectors for high energy particle physics and SEU radiation tests for ATLAS Inner Tracker Upgrade readout chip

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    This thesis covers the characterisation results and the design of monolithic CMOS detectors designed in TowerJazz 180nm CMOS technology for High Energy Particle Physics applications. Three different detectors have been studied the MALTA, the Mini-MALTA and the MALTA2. The MALTA sensor showed some efficiency losses at the corners of the pixels after irradiation, which meant that it was not suitable for the radiation environments in which it was supposed to be installed. Therefore, the front-end electronics and the fabrication process were modified to overcome this issue. The Mini-MALTA prototype was designed including the above mentioned improvements, fabricated and fully characterised. Finally taking into account all the knowledge acquired during these years of developments another large scale sensor the MALTA2 has been produced which should be radiation tolerant and have very good time resolution. The description and studies of the different architectures used in this family of detectors are covered and a simulation to estimate the bandwidth capabilities have been reported. Furthermore, this work will present characterisation of single event effects in the ITkPixV1, the prototype version of the ATLAS Inner Tracker Upgrade chip for the High Luminosity LHC. Measurements were made in testbeam campaigns with high energy ions and protons to evaluate the level of single event effects in the chip

    MorphStream: Scalable Processing of Transactions over Streams on Multicores

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    Transactional Stream Processing Engines (TSPEs) form the backbone of modern stream applications handling shared mutable states. Yet, the full potential of these systems, specifically in exploiting parallelism and implementing dynamic scheduling strategies, is largely unexplored. We present MorphStream, a TSPE designed to optimize parallelism and performance for transactional stream processing on multicores. Through a unique three-stage execution paradigm (i.e., planning, scheduling, and execution), MorphStream enables dynamic scheduling and parallel processing in TSPEs. Our experiment showcased MorphStream outperforms current TSPEs across various scenarios and offers support for windowed state transactions and non-deterministic state access, demonstrating its potential for broad applicability

    Radiation Tolerant Electronics, Volume II

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    Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

    Benchmark methodologies for the optimized physical synthesis of RISC-V microprocessors

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    As technology continues to advance and chip sizes shrink, the complexity and design time required for integrated circuits have significantly increased. To address these challenges, Electronic Design Automation (EDA) tools have been introduced to streamline the design flow. These tools offer various methodologies and options to optimize power, performance, and chip area. However, selecting the most suitable methods from these options can be challenging, as they may lead to trade-offs among power, performance, and area. While architectural and Register Transfer Level (RTL) optimizations have been extensively studied in existing literature, the impact of optimization methods available in EDA tools on performance has not been thoroughly researched. This thesis aims to optimize a semiconductor processor through EDA tools within the physical synthesis domain to achieve increased performance while maintaining a balance between power efficiency and area utilization. By leveraging floorplanning tools and carefully selecting technology libraries and optimization options, the CV32E40P open-source processor is subjected to various floorplans to analyze their impact on chip performance. The employed techniques, including multibit components prefer option, multiplexer tree prefer option, identification and exclusion of problematic cells, and placement blockages, lead to significant improvements in cell density, congestion mitigation, and timing. The optimized synthesis results demonstrate a 71\% enhancement in chip design performance without a substantial increase in area, showcasing the effectiveness of these techniques in improving large-scale integrated circuits' performance, efficiency, and manufacturability. By exploring and implementing the available options in EDA tools, this study demonstrates how the processor's performance can be significantly improved while maintaining a balanced and efficient chip design. The findings contribute valuable insights to the field of electronic design automation, offering guidance to designers in selecting suitable methodologies for optimizing processors and other integrated circuits

    Understanding the role of value in coral reef science

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    This thesis explores the role of value in coral science from the perspective of philosophy of science in practice. More specifically, it looks at the epistemology of different practices and theories in coral science, particularly how they interact with various forms of value, and how these forms of value can be understood. The arguments are organised into five chapters, which all make use of data collected in interviews with coral scientists, as well as ideas from coral science literature. The first presents an examination of ecological baselines, which I show do not simply ‘shift’ as has been supposed, but vary for a variety of reasons. This raises a question I address in the second chapter: when is this variation considered legitimate? The answer depends on the value of different reef states being considered. After showing how coral scientists navigate this in practice, I move on to the next two chapters where I explore areas of coral science where important forms of valuation take place: first, the value frameworks of intrinsic value and ecosystem services; and second, the use of bioacoustic techniques to assess reef health from non-human perspectives. These offer examples of how different forms of value shape coral science and make it relevant to the lifeforms practising and influenced by it. In the final chapter I present a view of coral science as a form of multispecies niche construction, both in the lab and the field. On this view, coral science is aimed at the flourishing of a range of living systems. This offers a better understanding of science-value interactions in socio-ecological contexts, such as when faced with decisions about baselines and interventions designed around these. Understanding how to navigate such situations is likely to become increasingly important as the challenges of surviving as a species continue to mount.Economic and Social Research Council (ESRC

    A Low Power, Rad-Hard, ECL Standard Cell Library

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    Space exploration for life both inside and outside of our solar system demand the design and fabrication of robust, reliable electronics that can take measurements, process data, and sustain necessary operations. However, the presence of high radiation and the cold temperature of space poses a challenge to most designers. This thesis presents the design of a radiation-hardened, cold capable emitter coupled logic standard cell library with the intention of being used for space applications. The cells are designed and fabricated in a 90nm silicon germanium BiCMOS process. First, a review of emitter coupled logic is presented. Then, the design methodology for the standard cells are presented. Next, the results of several fabricated standard cells are discussed and analyzed. Finally, the work is concluded and future work is discussed

    DESIGN MODULAR COMMAND AND DATA HANDLING SUBSYSTEM HARDWARE ARCHITECTURES

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    Over the past few years, On-Board Computing Systems for satellites have been facing a limited level of modularity. Modularity is the ability to reuse and reconstruct the system from a set of predesigned units, with minimal additional engineering effort. CDHS hardware systems currently available have a limited ability to scale with mission needs. This thesis addresses the integration of smaller form factor CDHS modules used for nanosatellites with the larger counterparts that are used for larger missions. In particular, the thesis discusses the interfacing between Modular Computer Systems based on Open Standard commonly used in large spacecrafts and PC/104 used for nanosatellites. It also aims to create a set of layers that would represent a hardware library of COTS-like modules. At the beginning, a review of related and previous work has been done to identify the gaps in previous studies and understand more about Modular Computer Systems based on Open Standard commonly used in large spacecrafts, such as cPCI Serial Space and SpaceVPX. Next, the design requirements have been set to achieve this thesis objectives, which included conducting a prestudy of system alternatives before creating a modular CDHS hardware architecture which was later tested. After, the hardware suitable for this architecture based on the specified requirements was chosen and the PCB was designed based on global standards. Later, several functional tests and communication tests were conducted to assess the practicality of the proposed architecture. Finally, thermal vacuum testing was done on one of the architecture’s layers to test its ability to withstand the space environment, with the aim to perform the vibration testing of the full modular architecture in the future. The aim of this thesis has been achieved after going through several tests, comparing between interfaces, and understanding the process of interfacing between different levels of the CDHS. The findings of this study pave the way for future research in the field and offer valuable insights that could contribute to the development of modular architectures for other satellite subsystems

    Stream Processor Development using Multi-Threshold NULL Convention Logic Asynchronous Design Methodology

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    Decreasing transistor feature size has led to an increase in the number of transistors in integrated circuits (IC), allowing for the implementation of more complex logic. However, such logic also requires more complex clock tree synthesis (CTS) to avoid timing violations as the clock must reach many more gates over larger areas. Thus, timing analysis requires significantly more computing power and designer involvement than in the past. For these reasons, IC designers have been pushed to nix conventional synchronous (SYNC) architecture and explore novel methodologies such as asynchronous, self-timed architecture. This dissertation evaluates the nominal active energy, voltage-scaled active energy, and leakage power dissipation across two cores of a stream processor: Smoothing Filter (SF) and Histogram Equalization (HEQ). Both cores were implemented in Multi-Threshold NULL Convention Logic (MTNCL) and clock-gated synchronous methodologies using a gate-level netlist to avoid any architectural discrepancies while guaranteeing impartial comparisons. MTNCL designs consumed more active energy than their synchronous counterparts due to the dual-rail encoding system; however, high-threshold-voltage (High-Vt) transistors used in MTNCL threshold gates reduced leakage power dissipation by up to 227%. During voltage-scaling simulations, MTNCL circuits showed a high level of robustness as the output results were logically valid across all voltage sweeps without any additional circuitry. SYNC circuits, however, needed extra logic, such as a DVS controller, to adjust the circuit’s speed when VDD changed. Although SYNC circuits still consumed less average energy, MTNCL circuit power gains accelerated when switching to lower voltage domains
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