Resource allocation technique for powerline network using a modified shuffled frog-leaping algorithm

Resource allocation (RA) techniques should be made efficient and optimized in order to enhance the QoS (power & bit, capacity, scalability) of high-speed networking data applications. This research attempts to further increase the efficiency towards near-optimal performance. RA’s problem involves assignment of subcarriers, power and bit amounts for each user efficiently. Several studies conducted by the Federal Communication Commission have proven that conventional RA approaches are becoming insufficient for rapid demand in networking resulted in spectrum underutilization, low capacity and convergence, also low performance of bit error rate, delay of channel feedback, weak scalability as well as computational complexity make real-time solutions intractable. Mainly due to sophisticated, restrictive constraints, multi-objectives, unfairness, channel noise, also unrealistic when assume perfect channel state is available. The main goal of this work is to develop a conceptual framework and mathematical model for resource allocation using Shuffled Frog-Leap Algorithm (SFLA). Thus, a modified SFLA is introduced and integrated in Orthogonal Frequency Division Multiplexing (OFDM) system. Then SFLA generated random population of solutions (power, bit), the fitness of each solution is calculated and improved for each subcarrier and user. The solution is numerically validated and verified by simulation-based powerline channel. The system performance was compared to similar research works in terms of the system’s capacity, scalability, allocated rate/power, and convergence. The resources allocated are constantly optimized and the capacity obtained is constantly higher as compared to Root-finding, Linear, and Hybrid evolutionary algorithms. The proposed algorithm managed to offer fastest convergence given that the number of iterations required to get to the 0.001% error of the global optimum is 75 compared to 92 in the conventional techniques. Finally, joint allocation models for selection of optima resource values are introduced; adaptive power and bit allocators in OFDM system-based Powerline and using modified SFLA-based TLBO and PSO are propose

Fast and Robust Design of CMOS VCO for Optimal Performance

The exponentially growing design complexity with technological advancement calls for a large scope in the analog and mixed signal integrated circuit design automation. In the automation process, performance optimization under different environmental constraints is of prime importance. The analog integrated circuits design strongly requires addressing multiple competing performance objectives for optimization with ability to find global solutions in a constrained environment. The integrated circuit (IC) performances are significantly affected by the device, interconnect and package parasitics. Inclusion of circuit parasitics in the design phase along with performance optimization has become a bare necessity for faster prototyping. Besides this, the fabrication process variations have a predominant effect on the circuit performance, which is directly linked to the acceptability of manufactured integrated circuit chips. This necessitates a manufacturing process tolerant design. The development of analog IC design methods exploiting the computational intelligence of evolutionary techniques for optimization, integrating the circuit parasitic in the design optimization process in a more meaningful way and developing process fluctuation tolerant optimal design is the central theme of this thesis. Evolutionary computing multi-objective optimization techniques such as Non-dominated Sorting Genetic Algorithm-II and Infeasibility Driven Evolutionary Algorithm are used in this thesis for the development of parasitic aware design techniques for analog ICs. The realistic physical and process constraints are integrated in the proposed design technique. A fast design methodology based on one of the efficient optimization technique is developed and an extensive worst case process variation analysis is performed. This work also presents a novel process corner variation aware analog IC design methodology, which would effectively increase the yield of chips in the acceptable performance window. The performance of all the presented techniques is demonstrated through the application to CMOS ring oscillators, current starved and xi differential voltage controlled oscillators, designed in Cadence Virtuoso Analog Design Environment

Multiprocessor System-on-Chips based Wireless Sensor Network Energy Optimization

Wireless Sensor Network (WSN) is an integrated part of the Internet-of-Things (IoT) used to monitor the physical or environmental conditions without human intervention. In WSN one of the major challenges is energy consumption reduction both at the sensor nodes and network levels. High energy consumption not only causes an increased carbon footprint but also limits the lifetime (LT) of the network. Network-on-Chip (NoC) based Multiprocessor System-on-Chips (MPSoCs) are becoming the de-facto computing platform for computationally extensive real-time applications in IoT due to their high performance and exceptional quality-of-service. In this thesis a task scheduling problem is investigated using MPSoCs architecture for tasks with precedence and deadline constraints in order to minimize the processing energy consumption while guaranteeing the timing constraints. Moreover, energy-aware nodes clustering is also performed to reduce the transmission energy consumption of the sensor nodes. Three distinct problems for energy optimization are investigated given as follows: First, a contention-aware energy-efficient static scheduling using NoC based heterogeneous MPSoC is performed for real-time tasks with an individual deadline and precedence constraints. An offline meta-heuristic based contention-aware energy-efficient task scheduling is developed that performs task ordering, mapping, and voltage assignment in an integrated manner. Compared to state-of-the-art scheduling our proposed algorithm significantly improves the energy-efficiency. Second, an energy-aware scheduling is investigated for a set of tasks with precedence constraints deploying Voltage Frequency Island (VFI) based heterogeneous NoC-MPSoCs. A novel population based algorithm called ARSH-FATI is developed that can dynamically switch between explorative and exploitative search modes at run-time. ARSH-FATI performance is superior to the existing task schedulers developed for homogeneous VFI-NoC-MPSoCs. Third, the transmission energy consumption of the sensor nodes in WSN is reduced by developing ARSH-FATI based Cluster Head Selection (ARSH-FATI-CHS) algorithm integrated with a heuristic called Novel Ranked Based Clustering (NRC). In cluster formation parameters such as residual energy, distance parameters, and workload on CHs are considered to improve LT of the network. The results prove that ARSH-FATI-CHS outperforms other state-of-the-art clustering algorithms in terms of LT.University of Derby, Derby, U

Recent Development of Hybrid Renewable Energy Systems

Abstract: The use of renewable energies continues to increase. However, the energy obtained from renewable resources is variable over time. The amount of energy produced from the renewable energy sources (RES) over time depends on the meteorological conditions of the region chosen, the season, the relief, etc. So, variable power and nonguaranteed energy produced by renewable sources implies intermittence of the grid. The key lies in supply sources integrated to a hybrid system (HS)

The 1st International Electronic Conference on Chemical Sensors and Analytical Chemistry

The 1st International Electronic Conference on Chemical Sensors and Analytical Chemistry was held on 1–15 July 2021. The scope of this online conference was to gather experts that are well-known worldwide who are currently working in chemical sensor technologies and to provide an online forum for the presention and discussion of new results. Throughout this event, topics of interest included, but were not limited to, the following: electrochemical devices and sensors; optical chemical sensors; mass-sensitive sensors; materials for chemical sensing; nano- and micro-technologies for sensing; chemical assays and validation; chemical sensor applications; analytical methods; gas sensors and apparatuses; electronic noses; electronic tongues; microfluidic devices; lab-on-a-chip; single-molecule sensing; nanosensors; and medico-diagnostic testing