Dynamic Virtual Page-based Flash Translation Layer with Novel Hot Data Identification and Adaptive Parallelism Management

Solid-state disks (SSDs) tend to replace traditional motor-driven hard disks in high-end storage devices in past few decades. However, various inherent features, such as out-of-place update [resorting to garbage collection (GC)] and limited endurance (resorting to wear leveling), need to be reduced to a large extent before that day comes. Both the GC and wear leveling fundamentally depend on hot data identification (HDI). In this paper, we propose a hot data-aware flash translation layer architecture based on a dynamic virtual page (DVPFTL) so as to improve the performance and lifetime of NAND flash devices. First, we develop a generalized dual layer HDI (DL-HDI) framework, which is composed of a cold data pre-classifier and a hot data post-identifier. Those can efficiently follow the frequency and recency of information access. Then, we design an adaptive parallelism manager (APM) to assign the clustered data chunks to distinct resident blocks in the SSD so as to prolong its endurance. Finally, the experimental results from our realized SSD prototype indicate that the DVPFTL scheme has reliably improved the parallelizability and endurance of NAND flash devices with improved GC-costs, compared with related works.Peer reviewe

System and Process for Providing Auxiliary Information for a Packet-Switched Network of Shared Nodes Using Dedicated Associative Store

A system and process for providing auxiliary information about a distributed network of shared nodes, at least a plurality of the nodes being adapted for receiving at least one type of ESP-(associative ephemeral store processing) packet. Available for access at each of the plurality of ESP-adapted nodes is a dedicated associative store wherein a value, if bound to a tag, is only accessible as a bound (tag, value) pair for a short time period, τ. Different types of packets are contemplated for routing through the ESP-capable plurality of nodes such as those arbitrarily identified herein as a ‘first’ and ‘second’ type: each first type packet has at least one field comprising an opcode identifying an instruction, and a tag; each second type packet has an opcode identifying an instruction an LOC field containing an identifier of a location for execution of an operand by the second packet instruction at any one of the ESP-capable plurality of nodes. In another aspect, each of the ESP-capable plurality of nodes has input and output port units and a centralized unit; an associative store may be dedicated to one or more of the port units as well as to the centralized location

Fabric-on-a-Chip: Toward Consolidating Packet Switching Functions on Silicon

The switching capacity of an Internet router is often dictated by the memory bandwidth required to bu¤er arriving packets. With the demand for greater capacity and improved service provisioning, inherent memory bandwidth limitations are encountered rendering input queued (IQ) switches and combined input and output queued (CIOQ) architectures more practical. Output-queued (OQ) switches, on the other hand, offer several highly desirable performance characteristics, including minimal average packet delay, controllable Quality of Service (QoS) provisioning and work-conservation under any admissible traffic conditions. However, the memory bandwidth requirements of such systems is O(NR), where N denotes the number of ports and R the data rate of each port. Clearly, for high port densities and data rates, this constraint dramatically limits the scalability of the switch. In an effort to retain the desirable attributes of output-queued switches, while significantly reducing the memory bandwidth requirements, distributed shared memory architectures, such as the parallel shared memory (PSM) switch/router, have recently received much attention. The principle advantage of the PSM architecture is derived from the use of slow-running memory units operating in parallel to distribute the memory bandwidth requirement. At the core of the PSM architecture is a memory management algorithm that determines, for each arriving packet, the memory unit in which it will be placed. However, to date, the computational complexity of this algorithm is O(N), thereby limiting the scalability of PSM switches. In an effort to overcome the scalability limitations, it is the goal of this dissertation to extend existing shared-memory architecture results while introducing the notion of Fabric on a Chip (FoC). In taking advantage of recent advancements in integrated circuit technologies, FoC aims to facilitate the consolidation of as many packet switching functions as possible on a single chip. Accordingly, this dissertation introduces a novel pipelined memory management algorithm, which plays a key role in the context of on-chip output- queued switch emulation. We discuss in detail the fundamental properties of the proposed scheme, along with hardware-based implementation results that illustrate its scalability and performance attributes. To complement the main effort and further support the notion of FoC, we provide performance analysis of output queued cell switches with heterogeneous traffic. The result is a flexible tool for obtaining bounds on the memory requirements in output queued switches under a wide range of tra¢ c scenarios. Additionally, we present a reconfigurable high-speed hardware architecture for real-time generation of packets for the various traffic scenarios. The work presented in this thesis aims at providing pragmatic foundations for designing next-generation, high-performance Internet switches and routers

The Effects of Closed Head Injury on the Learnability of Blissymbols

This study attempted to determine the effects of cognitive-communicative functioning in individuals who have sustained closed head injury on learnability of Blissymbols. Two features of Blissymbols, translucency and complexity, were examined to find their effects on Blissymbol learnability. Another focus of the study was to determine the effects of translucency and complexity interaction on learnability. The final research question concerned the relationship of cognitive-communicative functioning and Blissymbol learnability. Nine Subject, each rated with the Ranch Los Amigo Scale of Cognitive Functioning, participated in a task that required learning forty Blissymbols in a paired-associative learning task. The subjects were divided into three groups; Group One contained Level III/IV subjects, Group Two contained Level V/VI subjects, and Group Three contained Level VII/VIII subjects. Forty Blissymbols utilized in this study encompassed four conditions: 1) high translucency-high complexity (HTHC), 2) high translucency-low complexity (HTLC), 3) low translucency-high complexity (LTHC), and 4) low translucency-low complexity (LTLC). Each condition was represented by ten symbols. Subjects were required to point to each symbol five times as the label was called orally. Results showed a significant main effect for translucency, indicating that more high translucency symbols were learned than low translucency symbols. The effects of complexity and the translucency by complexity interaction were not found to be significant. No significant within group differences were found. Differences between trials were significant and post hoc analyses revealed that the means in Trials One and Two were significantly lower than Trials Three, Trials Four, and Trials Five. Limitations and implications of this investigation were discussed