379 research outputs found

    Low-Power Energy Efficient Circuit Techniques for Small IoT Systems

    Full text link
    Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology scaling has decreased circuit size, power usage and cost. This trend has led to the development of many small sensor systems with affordable costs and diverse functions, offering people convenient connection with and control over their surroundings. This dissertation discusses the major challenges and their solutions in realizing small IoT systems, focusing on non-digital blocks, such as power converters and analog sensing blocks, which have difficulty in following the traditional scaling trends of digital circuits. To accommodate the limited energy storage and harvesting capacity of small IoT systems, this dissertation presents an energy harvester and voltage regulators with low quiescent power and good efficiency in ultra-low power ranges. Switched-capacitor-based converters with wide-range energy-efficient voltage-controlled oscillators assisted by power-efficient self-oscillating voltage doublers and new cascaded converter topologies for more conversion ratio configurability achieve efficient power conversion down to several nanowatts. To further improve the power efficiency of these systems, analog circuits essential to most wireless IoT systems are also discussed and improved. A capacitance-to-digital sensor interface and a clocked comparator design are improved by their digital-like implementation and operation in phase and frequency domain. Thanks to the removal of large passive elements and complex analog blocks, both designs achieve excellent area reduction while maintaining state-of-art energy efficiencies. Finally, a technique for removing dynamic voltage and temperature variations is presented as smaller circuits in advanced technologies are more vulnerable to these variations. A 2-D simultaneous feedback control using an on-chip oven control locks the supply voltage and temperature of a small on-chip domain and protects circuits in this locked domain from external voltage and temperature changes, demonstrating 0.0066 V/V and 0.013 °C/°C sensitivities to external changes. Simple digital implementation of the sensors and most parts of the control loops allows robust operation within wide voltage and temperature ranges.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138743/1/wanyeong_1.pd

    Digitally Controlled Envelope Tracking Power Supply for an RF Power Amplifier

    Get PDF

    Design and Implementation of a Novel Flash ADC for Ultra Wide Band Applications

    Get PDF
    This dissertation presents a design and implementation of a novel flash ADC architecture for ultra wide band applications. The advancement in wireless technology takes us in to a world without wires. Most of the wireless communication systems use digital signal processing to transmit as well as receive the information. The real world signals are analog. Due to the processing complexity of the analog signal, it is converted to digital form so that processing becomes easier. The development in the digital signal processor field is rapid due to the advancement in the integrated circuit technology over the last decade. Therefore, analog-to -digital converter acts as an interface in between analog signal and digital signal processing systems. The continuous speed enhancement of the wireless communication systems brings out huge demands in speed and power specifications of high-speed low-resolution analog-to -digital converters. Even though wired technology is a primary mode of communication, the quality and efficiency of the wireless technology allows us to apply to biomedical applications, in home services and even to radar applications. These applications are highly relying on wireless technology to send and receive information at high speed with great accuracy. Ultra Wideband (UWB) technology is the best method to these applications. A UWB signal has a bandwidth of minimum 500MHz or a fractional bandwidth of 25 percentage of its centre frequency. The two different technology standards that are used in UWB are multiband orthogonal frequency division multiplexing ultra wideband technology (MB-OFDM) and carrier free direct sequence ultra wideband technology (DS-UWB). ADC is the core of any UWB receiver. Generally a high speed flash ADC is used in DS-UWB receiver. Two different flash ADC architectures are proposed in this thesis for DS-UWB applications. The first design is a high speed five bit flash ADC architecture with a sampling rate of 5 GS/s. The design is verified using CADENCE tool with CMOS 90 nm technology. The total power dissipation of the ADC is 8.381 mW from power supply of 1.2 V. The die area of the proposed flash ADC is 186 μm × 210 μm (0.039 mm2). The proposed flash ADC is analysed and compared with other papers in the literature having same resolution and it is concluded that it has the highest speed of operation with medium power dissipation. iii The second design is a reconfigurable five bit flash ADC architecture with a sampling rate of 1.25 GS/s. The design is verified using CADENCE tool with UMC 180 nm technology. The total power dissipation of the ADC is 11.71 mW from power supply of 1.8 V. The die area of the implementation is 432 μm × 720 μm (0.31104 mm2). The chip tape out of the proposed reconfigurable flash ADC is made for fabrication

    Data Conversion Within Energy Constrained Environments

    Get PDF
    Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

    An Energy Efficient Power Converter for Zero Power Wearable Devices

    Get PDF
    Early diagnosis of Alzheimer's and epilepsy requires monitoring a subject's development of symptoms through electroencephalography (EEG) signals over long periods. Wearable devices enable convenient monitoring of biosignals, unlike complex and costly hospital equipment. The key to achieving a fit and forgettable wearable device is to increase its operating cycle and decrease its size and weight. Instead of batteries, which limit the life cycle of electronic devices and set their form factor, body heat and environmental light can power wearable devices through energy-scavenging technologies. The harvester transducers should be tailored according to on the application and the sensor placement. This leaves a wide variety of transducers with an extensive range of impedances and voltages. To realize an autonomous wearable device, the power converter energy harvester, has to be very efficient and maintain its efficiency despite potential transducer replacement or variations in environmental conditions. This thesis presents a detailed design of an efficient integrated power converter for use in an autonomous wearable device. The design is based on the examination of both power losses and power transfer in the power converter. The efficiency bound of the converter is derived from the specifications of its transducer. The tuning ranges for the reconfigurable parameters are extracted to keep the converter efficient with variations in the transducer specifications. With the efficient design and the manual tuning of the reconfigurable parameters, the converter can work optimally with different types of transducers, and keeps its efficiency in the conversion of low voltages from the harvesters. Measurements of the designed converter demonstrate an efficiency of higher than 50% and 70% with two different transducers having an open-circuit voltage as low as 20 mV and 100 mV, respectively. The power converter should be able to reconfigure itself without manual tunings to keep its efficiency despite changes in the harvesters' specifications. The second portion of this dissertation addresses this issue with a proposed design methodology to implement a control section. The control section adjusts the converter's reconfigurable parameters by examining the power transfer and loss and through concurrent closed loops. The concurrent loops working together raise a serious concern regarding stability. The system is designed and analyzed in the time domain with the state-space averaging (SSA) model to address the stability issue. The ultra-low-power control section obtained from the SSA model estimates the power and loss with a reasonable accuracy, and adjusts the timings in a stable manner. The entire control section consumes only 30 nW dynamic power at 10 kHz. The control section tunes the converter's speed or its working frequency depending on the available power. The frequency clocks the entire architecture, which is designed asynchronously; therefore, the power consumption of the system depends on the power available from the transducer. The system is implemented using 0.18 µm CMOS technology. For an input as low as 7 mV, the converter is not only functional but also has an efficiency of more than 40%. The efficiency can reach 70% with an input voltage of 50 mV. The system operates in a range of just a few of millivolts to half a volt with ample efficiencies. It can work at an optimal point with different transducers and environmental conditions

    Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

    Get PDF
    This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

    Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

    Get PDF
    This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

    A novel control mechanism for hybrid 5-level DC-DC converter for higher switching frequency and lower voltage ripple

    Get PDF
    The introduction and development of hybrid DC-DC converters present a valuable opportunity in on-chip power management, as they combine the advantages of buck and switched-capacitor converters while alleviating shortcomings such as conversion efficiency and sizing requirements. In this paper, a new control methodology is presented for the recently developed 5-level hybrid DC-DC converter, which utilizes the Virtex 5 LX50T FPGA to drive the converter. This control method allows for a higher switching frequency of 1MHz and an improved conversion efficiency while also allowing for dynamic voltage control based on the desired output voltage. Simulations as well as a test circuit are used to illustrate the proper control functionality, with tabulated results that showcase the efficiency advantage over prior control methods as well as the buck and 3-level hybrid converters

    Low power dynamic comparator design

    Get PDF
    In many applications there is a growing demand for the development of low voltage and low power circuits and systems. Low power consumption is of great interest because it increases the battery lifetime. One of the main building blocks in many applications is the analogue-to-digital converter (ADC) which serves as an interface between the analogue world and the digital processing unit. In all these designs the comparator of the ADC, which is one the most power hungry blocks, is always on. In order to reduce the power consumption of the ADC it is possible to turn the comparator off when the decision is made and the comparator is not needed until the next clock cycle. This work provides a comprehensive review about a variety of comparator designs - in terms of performance, power and delay. The initial part of the work was working with static comparators architectures with different pre-amplifier modifications .Later part deals with two dynamic comparator architectures. The main components of such comparators are the preamplifier and latch circuit. Preamplifier is used for removing the kickback noise and the dc offset voltage while the latch is required for the comparison. The proposed architectures operate on three phases which are non-overlapping and dissipate 7ìW power when operated on a single 1V supply voltage. The latch is basically a back to back connected inverter circuit which inactivated only during the second phase
    corecore