A DLL Based Test Solution for 3D ICs

Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations have obvious advantages over the conventional two dimensional IC implementations in performance, capacity, and power consumption. A passive Si interposer utilizing Through-Silicon via (TSV) technology is used for 2.5D IC integration. TSV is also the enabling technology for 3D IC integration. TSV manufacturing defects can affect the performance of stacked devices and reduce the yield. Manufacturing test methodologies for TSVs have to be developed to ensure fault-free devices. This thesis presents two test methods for TSVs in 2.5D and 3D ICs utilizing Delay-Locked Loop (DLL) modules. In the test method developed for TSVs in 2.5D ICs, a DLL is used to determine the propagation delay for fault detection. TSV faults in 3D ICs are detected through observation of the control voltage of a DLL. The proposed test methods present a robust performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLLs. 3D full-wave simulations are performed to extract circuit level models for TSVs and fragments of an interposer wires using HFSS simulation tools. The extracted TSV models are then used to perform circuit level simulations using ADS tools from Agilent. Simulation results indicate that the proposed test solution for TSVs can detect manufacturing defects affecting the TSV propagation delay

Embedding and assembly of ultrathin chips in multilayer flex boards

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Purpose – The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips. Design/methodology/approach – Methods to embed chips in flex include flip-chip assembly and subsequent lamination, or the construction of a separate ultra-thin chip package (UTCP) using spin-on polyimides and thin-film metallisation technology. Thinning and separation of the chips is done using a “dicing-by-thinning” method. Findings – The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 mm package where also the 20mm thick chip is bendable. Research limitations/implications – Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demonstrators using the developed technologies. Originality/value – Thinning down silicon chips to thicknesses of 25mm and lower is an innovative technology, as well as assembly and embedding of these chips in flexible substrates.EC/FP6/EU/507745/Smart high-integration flex technologies/SHIF

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Investigation into yield and reliability enhancement of TSV-based three-dimensional integration circuits

Three dimensional integrated circuits (3D ICs) have been acknowledged as a promising technology to overcome the interconnect delay bottleneck brought by continuous CMOS scaling. Recent research shows that through-silicon-vias (TSVs), which act as vertical links between layers, pose yield and reliability challenges for 3D design. This thesis presents three original contributions.The first contribution presents a grouping-based technique to improve the yield of 3D ICs under manufacturing TSV defects, where regular and redundant TSVs are partitioned into groups. In each group, signals can select good TSVs using rerouting multiplexers avoiding defective TSVs. Grouping ratio (regular to redundant TSVs in one group) has an impact on yield and hardware overhead. Mathematical probabilistic models are presented for yield analysis under the influence of independent and clustering defect distributions. Simulation results using MATLAB show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratio results in achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios. The second contribution presents an efficient online fault tolerance technique based on redundant TSVs, to detect TSV manufacturing defects and address thermal-induced reliability issue. The proposed technique accounts for both fault detection and recovery in the presence of three TSV defects: voids, delamination between TSV and landing pad, and TSV short-to-substrate. Simulations using HSPICE and ModelSim are carried out to validate fault detection and recovery. Results show that regular and redundant TSVs can be divided into groups to minimise area overhead without affecting the fault tolerance capability of the technique. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case). The last contribution proposes a technique with joint consideration of temperature mitigation and fault tolerance without introducing additional redundant TSVs. This is achieved by reusing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs. The proposed technique consists of two steps: TSV determination step, which is for achieving optimal partition between regular and spare TSVs into groups; The second step is TSV placement, where temperature mitigation is targeted while optimizing total wirelength and routing difference. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 75.2? (34.1%) (best case is 99.8? (58.5%)), while increasing wirelength by a small amount

Development, Characterization, and Analysis of Silicon Microstrip Detector Modules for the CBM Silicon Tracking System

The future Facility for Antiproton and Ion Research (FAIR) at GSI, Germany, will enable scientists to create tiny droplets of cosmic matter in the laboratory—matter subject to extreme conditions usually found in the interior of stars or during stellar collisions. The Compressed Baryonic Matter (CBM) experiment at FAIR aims to explore the quantum chromodynamics (QCD) phase diagram at high densities and moderate temperatures. By colliding heavy ions at relativistic beam energies, the conditions inside these supermassive objects can be recreated for an exceptionally short amount of time. The CBM detector is a fixed-target multi-purpose detector designed for measuring hadrons, electrons and muons in elementary nucleon and heavy-ion collisions over the full FAIR beam energy range delivered by the SIS100 synchrotron. One of the core detectors of CBM is the Silicon Tracking System (STS), responsible for measuring the momentum and tracks of up to 700 charged particles produced in a central nucleus-nucleus collisions. Due to the required momentum resolution, the material budget of the STS must be minimized. Therefore, the readout electronics and the cooling and mechanical infrastructure are placed out of the detector acceptance. The double-sided silicon microstrip sensors are connected to the self-triggering frontend electronics using low-mass flexible microcables with a length of up to 50 cm. The main goal of this thesis was to develop a high-density interconnection technology based on copper microcables. We developed a low-mass double-layered copper microcable at the edge of modern fabrication technology. Based on the copper microcable, we developed a novel high-density interconnection technology, comprising fine-grain solder paste printing on the microcable and gold stud bumping on the die. The gold stud--solder technology combines a high automation capability with good mechanical and electrical properties, making it an interesting technology also for future detector systems. Building on the gold stud--solder technology, a fully customized bonder machine was developed and constructed in hardware and software. Its main purpose is the realization of the challenging interconnection between the microcable and the sensor. Key components of the machine are four step motors with a sub-micron step resolution, a dual-camera pattern recognition system, a heatable, temperature-controlled bond head and sensor plate, as well as tailor-made mechanical supports for the STS detector modules. With the help of this bonder machine, a full-scale STS detector module in the copper technology was built. The noise performance of the copper module was evaluated in a bias voltage scan. Very low noise levels were observed. Measurements of the absolute value of the signal with a radioactive source allowed us to estimate the signal-to-noise ratio of the module. The results of these measurements give us confidence that STS modules based on the copper technology can achieve a satisfying performance comparable to the modules built in the aluminium technology. Another essential component of the STS detector module is the frontend electronics chip. During this work, the version 2.1 of the STS-XYTER readout ASIC was extensively characterized. Noise discrepancies between odd and even channels and increasingly higher noise towards the higher channel numbers had been observed in the predecessor chip. Our measurements of the STS-XYTER2.1 verified that both issues were successfully resolved. Furthermore, the noise behavior of the ASIC with respect to input load capacitance was studied. This is essential to parametrize expected noise levels for the many kinds of detector modules employed in the STS, to which the measured noise levels can then be compared. Measurements of the noise levels as a function of shaping time showed that the overall noise level is practically independent of shaper peaking time. Radiation tests with 50 MeV protons were performed with copper microcables connected to the ASIC in a non-powered state. No indications of damage to the chip and interconnects could be observed. Finally, a complete STS detector module in aluminium technology was subjected to a pencil-like monochromatic beam of 2.7 GeV/c protons at the Cooling Synchrotron at the research center Jülich. Several essential performance criteria of the detector module were evaluated. The best coincidence between the STS and the reference fiber hodoscopes was established based on time information. An excellent time resolution of a few nanoseconds could be demonstrated. Based on the best coincidence, the spatial resolution of the full system was determined to be a few hundred microns. This is in line with expectations, as the resolution is limited by the fiber hodoscope resolution. Charge distributions of 1-strip clusters showed a clear separation between the noise and the proton signal peak, with a signal-to-noise ratio above 20 for the p-- and n-side. The charge collection efficiency of the module was estimated to be $96 \%$. The COSY beamtime enabled a first-time evaluation of the full analysis software chain with real data and the evaluation of the full electronic readout chain of STS. The experience gained at COSY is immensely helpful for commissioning and data analysis in more complex beam environments such as mCBM, where a subsample of the CBM detectors is exposed to the particles created in a heavy-ion collision in run-time scenarios closely resembling the final CBM environment

Memory Hierarchy Design for Next Generation Scalable Many-core Platforms

Performance and energy consumption in modern computing platforms is largely dominated by the memory hierarchy. The increasing computational power in the multiprocessors and accelerators, and the emergence of the data-intensive workloads (e.g. large-scale graph traversal and scientific algorithms) requiring fast transfer of large volumes of data, are two main trends which intensify this problem by putting even higher pressure on the memory hierarchy. This increasing gap between computation speed and data transfer speed is commonly referred as the “memory wall” problem. With the emergence of heterogeneous Three Dimensional (3D) Integration based on through-silicon-vias (TSV), this situation has started to recover in the past years. On one hand, it is now possible to improve memory access bandwidth and/or latency by either stacking memories directly on top of processors or through abstracted memory interfaces such as Micron’s Hybrid Memory Cube (HMC). On the other hand, near memory computation has become worthy of revisiting due to the cost-effective integration of logic and memory in 3D stacks. These two directions bring about several interesting opportunities including performance improvement, energy and cost reduction, product miniaturization, and modular design for improved time to market. In this research, we study the effectiveness of the 3D integration technology and the optimization opportunities which it can provide in the different layers of the memory hierarchy in cluster-based many-core platforms ranging from intra-cluster L1 to inter-cluster L2 scratchpad memories (SPMs), as well as the main memory. In addition, by moving a part of the computation to where data resides, in the 3D-stacked memory context, we demonstrate further energy and performance improvement opportunities

Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception.In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

IN-SITU APPROACH FOR CHARACTERIZATION AND MODELING OF TRANSPONDER PACKAGING TECHNIQUES IN RADIO FREQUENCY INDENTIFICATION SYSTEMS

In a typical Radio Frequency Identification system, the tag-reader communication is the most important characteristic of success or failure. In this system, the tag represents the weakest link in the equation and must be selected with great care. It is also important to recognize that a passive RFID tag derives its power from the RF energy generated by the reader. In turn, it communicates to the reader by modulation of the incident RF energy to create a backscatter signal, where any power loss between the antenna and the integrated circuit chip limits the maximum distance from which the tag can be read. Because the typical assembly flow of the RFID labels requires multiple steps, different assembly methodologies are being used to lower the final cost of the RFID label. Packaged parasitic components can significantly degrade the performance of the RFID tags. Today, the most insidious problem is the loss of energy due to the mismatch between the antenna and the IC chip. The final cost and fabrication requirements for the RFID tag impose a set of criteria on the assembly of the tag, where the typical methods for extracting and characterizing parasitic components of the packaging are not feasible. This research develops the theoretical mechanism for measuring and modeling the packaging parasitic components of the passive Ultra High Frequency RFID tags. The research is based on proven antenna theory and antenna measurement methods, which in turn will provide a benchmark for the current and future assembly methods for manufacturing of the RFID labels