109 research outputs found

    Naval Postgraduate School Academic Catalog - February 2023

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    RF CMOS Oscillators for Modern Wireless Applications

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    While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

    A Bulk Driven Transimpedance CMOS Amplifier for SiPM Based Detection

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    The contribution of this work lies in the development of a bulk driven operationaltransconducctance amplifier which can be integrated with other analog circuits andphotodetectors in the same chip for compactness, miniaturization and reducing thepower. Silicon photomultipliers, also known as SiPMs, when coupled with scintillator materials are used in many imaging applications including nuclear detection. This thesis discuss the design of a bulk-driven transimpedance amplifier suitable for detectors where the front end is a SiPM. The amplifier was design and fabricated in a standard standard CMOS process and is suitable for integration with CMOS based SiPMs and commercially available SiPMs. Specifically, the amplifier was verified in simulations and experiment using circuit models for the SiPM. The bulk-driven amplifier’s performance, was compared to a commerciallyavailable amplifier with approximately the same open loop gain (70dB). Bothamplifiers were verified with two different light sources, a scintillator and a SiPM.The energy resolution using the bulk driven amplifier was 8.6% and was 14.2% forthe commercial amplifier indicating the suitability of the amplifier design for portable systems

    Naval Postgraduate School Academic Catalog - September 2022

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    Naval Postgraduate School Academic Catalog - 09 July 2021

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    Naval Postgraduate School Academic Catalog - September 2021

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    Energy Efficiency in Communications and Networks

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    The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

    ASIC para estimulação elétrica da espinal medula

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    Spinal Cord Injuries (SCI) have severe consequences such as tetraplegia and paraplegia, which dramatically affect the healthcare of the patients. Successful therapies for such injuries are yet to be attainable. Currently, there is a focus on the study and implementation of small implantable devices that are capable of providing in-vivo electrical stimulation to the spinal cord. Since the impedance of the neural tissue experiences constant changes, the focus is on using current stimulation instead of voltage, to compensate the impedance variations. Furthermore, the usage of scaffolds to provide alignment on the regrown fibers, combined with electrical stimulation is viewed as possible solution for SCI therapy. The NeuroStim- Spinal project, in which this work is inserted, aims to propose a SCI therapy based on in-vivo electrical stimulation combined with 3D printed scaffolds that have in its composition based materials (GBM) and adipose derived decellularized tissue (adECM). The work presented is an application-specific integrated circuit design (ASIC) that provides current-mode stimulation for neuronal regeneration, with the objective of providing in-vivo electrical stimulation for SCI therapy. The main challenges on the design of such devices is in obtaining low circuit area and power consumption, while maintaining the specifications needed. These characteristics are important, since it is intended to be an implantable device. The stimulation circuit consists of, a communication interface with a microcontroller using the Serial Peripheral Communication (SPI) protocol, a 10-bit DAC (Digital-to-Analog Converter) based on a binary charge scaling architecture, a voltage-to-current converter with a feed-forward voltage attenuator (FFVA) architecture, and a H-bridge circuit composed of CMOS switches to drive the scaffold. Results demonstrate that the system developed is capable of driving current from 0 to 200μA with an absolute error bellow 0.75μA. In addition, the developed circuit can provide these range of currents with high linearity to a 15k load impedance. The system can still provide linear stimulation for higher load impedance’s, but in smaller current ranges. Furthermore, the circuit uses a supply voltage of 5V and has an average power dissipation of 19.5mW. The ASIC was developed using a 0.35μm CMOS technology, has dimensions of 270μm per 700μm, which corresponds to a total area of 0.19mm2. The work was developed using the Cadence software.Lesões na Medula Espinhal são causadas sobretudo devido acidentes rodoviários, quedas e lesões na prática de desportos. Estas têm graves consequências no estado de saúde dos pacientes, uma vez que saõ responsáveis por diagnósticos como tetraplegia e paraplegia. Até hoje, terapias eficazes para este tipo de lesões ainda não foram conseguidas, o que torna esta temática num foco de estudo. Atualmente, uma das orientações deste foco de estudo está direcionado em dispositivos elétricos implantáveis capazes de estimular a espinal medula in-vivo, promovendo a regeneração da mesma. Adicionalmente, o uso de materiais (scaffolds) que permitem manter o alinhemento no crescimento das fibras, em conjunto com estimulação elétrica é vista como a solução consensual para terapias relacionadas com Lesões na Medula Espinhal. Assim, o projeto NeuroStimSpinal, na qual este trabalho se insere, foi proposto. Este tem como objetivo propor uma terapia para esta problemática usando estimulação elétrica em conjunto com scaffolds impressas em 3D. O trabalho apresentado nesta dissertação é baseado num circuito integrado de aplicação específica (CIAE) para estimulação em corrente da espinal medula, com o intuito de promover a regeneração da mesma. Os desafios na implementação deste tipo de circuitos estão relacionados com a necessidade destes terem de ser pequenos em tamanho e consumir uma potência reduzida, mantendo as características necessárias para a estimulação, uma vez que é necessário que o mesmo faça parte de um dispositivo implantável. O circuito de estimulação proposto consiste: numa interface de comunicação com a unidade de controlo (microcontrolador) usando o protocolo Serial Peripheral Communication (SPI); um conversor digital para analógico de 10 bits, o qual se baseia numa arquitetura de escalonamento binário por carga; um conversor tensão para corrente rail-to-rail e uma ponte H que direciona a corrente pela scaffold, cuja implementação se baseia no uso de portas de transmissão como comutadores. Resultados ao trabalho desenvolvido mostram que o circuito é capaz de estimular a scaffold com correntes entre 0 to 200μA com um erro na corrente de estimulação inferior a 0.75μA. O circuito é capaz ainda de fornecer uma corrente linear, na gama mencionada, a cargas com impedancias até 15k . Para cargas superiores o circuito é capaz de fornecer uma corrente linear, embora em gamas de correntes menores. O circuito implementado usa como tensão de alimentação 5V, tem um consumo médio de potência de 19.5mW e ocupa uma área de 0.19mm2. No decurso do trabalho desenvolvido foi utilizada uma tecnlogoia CMOS de 0.35um. A implementação e resultados foram obtidos com recurso ao software Cadence.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

    Naval Postgraduate School Academic Catalog - January 2021

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