Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems

This dissertation reports the development of a new multi-band multi-output synthesizer, 1/2 dual-injection locked divider, 1/3 injection-locked divider with phase-tuning, and 1/3 injection-locked divider with self-injection using 0.18-micrometer CMOS technology. The synthesizer is used for a multi-band multi-polarization radar system operating in the K- and Ka-band. The synthesizer is a fully integrated concurrent tri-band, tri-output phase-locked loop (PLL) with divide-by-3 injection locked frequency divider (ILFD). A new locking mechanism for the ILFD based on the gain control of the feedback amplifier is utilized to enable tunable and enhanced locking range which facilitates the attainment of stable locking states. The PLL has three concurrent multiband outputs: 3.47-4.313 GHz, 6.94-8.626 GHz and 19.44-21.42-GHz. High second-order harmonic suppression of 62.2 dBc is achieved without using a filter through optimization of the balance between the differential outputs. The proposed technique enables the use of an integer-N architecture for multi-band and microwave systems, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption. The 1/2 dual-ILFD with wide locking range and low-power consumption is analyzed and designed together with a divide-by-2 current mode logic (CML) divider. The 1/2 dual-ILFD enhances the locking range with low-power consumption through optimized load quality factor (QL) and output current amplitude (iOSC) simultaneously. The 1/2 dual-ILFD achieves a locking range of 692 MHz between 7.512 and 8.204 GHz. The new 1/2 dual-ILFD is especially attractive for microwave phase-locked loops and frequency synthesizers requiring low power and wide locking range. The 3.5-GHz divide-by-3 (1/3) ILFD consists of an internal 10.5-GHz Voltage Controlled Oscillator (VCO) functioning as an injection source, 1/3 ILFD core, and output inverter buffer. A phase tuner implemented on an asymmetric inductor is proposed to increase the locking range. The other divide-by-3 ILFD utilizes self-injection technique. The self-injection technique substantially enhances the locking range and phase noise, and reduces the minimum power of the injection signal needed for the 1/3 ILFD. The locking range is increased by 47.8 % and the phase noise is reduced by 14.77 dBc/Hz at 1-MHz offset