Reliable time exponents for long term prediction of negative bias temperature instability by extrapolation

To predict the negative bias temperature instability (NBTI) towards the end of pMOSFETs’ 10 years lifetime, power-law based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. The n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to 10 years. The objective of this work is to find how to make the n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps (AHT), a new method is proposed to capture the generated defects (GD) in their entirety. The n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under AC operation, the model predicts that GD can contribute to ~90% of NBTI at 10 years

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent device breakdown (TDDB). Among them, hot carrier aging (HCA) has attracted much attention recently, because it is limiting the device lifetime. As the channel length of MOSFETs becomes smaller, the lateral electrical field increases and charge carriers become sufficiently energetic (“hot”) to cause damage to the device when they travel through the space charge region near the drain. Unlike aging that causes device parameters, such as threshold voltage, to drift in one direction, nano-scale devices also suffer from Random Telegraph Noise (RTN), where the current can fluctuate under fixed biases. RTN is caused by capturing/emitting charge carriers from/to the conduction channel. As the device sizes are reduced to the nano-meters, a single trap can cause substantial fluctuation in the current and threshold voltage. Although early works on HCA and RTN have improved the understanding, many issues remain unresolved and the aim of this project is to address these issues. The project is broadly divided into three parts: (i) an investigation on the HCA kinetics and how to predict HCA-induced device lifetime, (ii) a study of the interaction between HCA and RTN, and (iii) developing a new technique for directly measuring the RTN-induced jitter in the threshold voltage. To predict the device lifetime, a reliable aging kinetics is indispensable. Although early works show that HCA follows a power law, there are uncertainties in the extraction of the time exponent, making the prediction doubtful. A systematic experimental investigation was carried out in Chapter 4 and both the stress conditions and measurement parameters were carefully selected. It was found that the forward saturation current, commonly used in early work for monitoring HCA, leads to an overestimation of time exponents, because part of the damaged region is screened off by the space charges near the drain. Another source of errors comes from the inclusion of as-grown defects in the aging kinetics, which is not caused by aging. This leads to an underestimation of the time exponent. After correcting these errors, a reliable HCA kinetics is established and its predictive capability is demonstrated. There is confusion on how HCA and RTN interact and this is researched into in Chapter 5. The results show that for a device of average RTN, HCA only has a modest impact on RTN. RTN can either increase or decrease after HCA, depending on whether the local current under the RTN traps is rising or reducing. For a device of abnormally high RTN, RTN reduces substantially after HCA and the mechanism for this reduction is explored. The RTN-induced threshold voltage jitter, ∆Vth, is difficult to measure, as it is typically small and highly dynamic. Early works estimate this ∆Vth from the change in drain current and the accuracy of this estimation is not known. Chapter 6 focuses on developing a new ‘Trigger-When-Charged’ technique for directly measuring the RTN-induced ∆Vth. It will be shown that early works overestimate ∆Vth by a factor of two and the origin of this overestimation is investigated. This thesis consists of seven chapters. Chapter 1 introduces the project and its objectives. A literature review is given in Chapter 2. Chapter 3 covers the test facilities, measurement techniques, and devices used in this project. The main experimental results and analysis are given in Chapters 4-6, as described above. Finally, Chapter 7 concludes the project and discusses future works

Probing technique for energy distribution of positive charges in gate dielectrics and its application to lifetime prediction

The continuous reduction of the dimensions of CMOS devices has increased the negative bias temperature instability (NBTI) of pMOSFETs to such a level that it is limiting their lifetime. This increase of NBTI is caused mainly by three factors: an increase of nitrogen concentration in gate dielectric, a higher operation electrical field, and a higher temperature. Despite of many years’ research work, there are questions on the correctness of the NBTI lifetime predicted through voltage acceleration and extrapolation. The conventional lifetime prediction technique measures the degradation slowly and it typically takes 10 ms or longer to record one threshold voltage shift. It has been reported that NBTI can recover substantially in this time and the degradation is underestimated. To minimize the recovery, ultra-fast technique has been developed and the measurement time has been reduced to the order of microseconds. Once the recovery is suppressed, however, the degradation no longer follows a power law and there is no industry-wide accepted method for lifetime prediction. The objective of this project is to overcome this challenge and to develop a reliable NBTI lifetime prediction technique after freezing the recovery. To achieve this objective, it is essential to have an in-depth knowledge on the defects responsible for the recovery. It has been generally accepted that the NBTI recovery is dominated by the discharge of trapped holes. For the thin dielectric (e.g. < 3 nm) used by current industry, all hole traps are within direct tunnelling distance from the substrate and their discharging is mainly controlled by their energy levels against the Fermi level at the substrate interface. As a result, it is crucial to have the energy distribution of positive charges (PC) in the gate dielectric, but there is no technique available for probing this energy profile. A major achievement of this project is to develop a new technique that can probe the energy distribution of PCs both within and beyond the silicon energy gap. After charging up the hole traps, they are allowed to discharge progressively by changing the gate bias, Vg, in the positive direction in steps. This allows the Fermi level at the interface to be swept from a level below the valence band edge to a level above the conduction band edge, giving the required energy profile. Results show that PCs can vary by one order of magnitude with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps which are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence band edge are from the created defects. The PCs within bandgap saturate for either longer stress time or higher stress temperature. In contrast, the PCs above conduction band edge, namely the anti-neutralization positive charges, do not saturate and their generation is clearly thermally accelerated. This energy profile technique is applicable to both SiON and high-k/SiON stack. It is found that both of them have a high level of as-grown hole traps below the valence band edge and their main difference is that there is a clear peak in the energy density near to the conduction band edge for the High-k/SiON stack, but not for the SiON. Based on this newly developed energy profile technique and the improved understanding, a new lifetime prediction technique has been proposed. The principle used is that a defect must be chargeable at an operation voltage, if it is to be included in the lifetime prediction. At the stress voltage, some as-grown hole traps further below Ev are charged, but they are neutral under an operation bias and must be excluded in the lifetime prediction. The new technique allows quantitative determination of the correct level of as-grown hole trapping to be included in the lifetime prediction. A main advantage of the proposed technique is that the contribution of as-grown hole traps is experimentally measured, avoiding the use of trap-filling models and the associated fitting parameters. The successful separation of as-grown hole trapping from the total degradation allows the extraction of generated defects and restores the power-law kinetics. Based on this new lifetime prediction technique, it is concluded that the maximum operation voltage for a 10 years lifetime is substantially overestimated by the conventional prediction technique. This new lifetime prediction technique has been accepted for presentation at the 2013 International Electron Devices Meeting (IEDM)

Bias Temperature Instability Modelling and Lifetime Prediction on Nano-scale MOSFETs

Bias Temperature Instability (BTI) is one of the most important reliability concerns for Metal Oxide Semiconductor Field Effect Transistors (MOSFET), the basic unit in integrated circuits. As the development MOSFET manufacturing technology, circuit designers need to consider device reliability during design optimization. An accurate BTI lifetime prediction methodology becomes a prerequisite. Typical BTI lifetime standard is ten years, accelerated BTI tests under high stress voltages are mandatory. BTI modelling is needed to project BTI lifetime from high voltages (accelerated condition) to operating voltage. The existing two mainstream BTI models: 1). The Reaction-Diffusion (R-D) framework and 2). The Two-Stage model cannot provide accurate lifetime prediction. Quite a few fitting parameters and unjustifiable empirical equations are needed in the R-D framework to predict the lifetime, questioning its predicting capability. The Two-stage model cannot project device lifetime from high voltages to operating voltage. Moreover, the scaling down of MOSFET feature size brings new challenges to nano-scale device lifetime prediction: 1). Nano-scale devices’ current is fluctuating due to the impact of a single charge is increasing as MOSFET scaling down, repetitive tests need to be done to achieve meaningful averaged results; 2). Nano-scale devices have significant Device-to-Device variability, making the lifetime a distribution instead of a single value. In this work a comprehensive As-grown Generation (A-G) framework based on the A-G model and defect centric theory is proposed and successfully predicts the Time Dependent Variability and lifetime on nano-scale devices. The predicting capability is validated by the good agreement between the test data and predicted values. It is speculated that the good predicting capability is due to the correct understanding of different types of defects. In the A-G framework, Time Dependent Variability is experimentally separated into Within-Device Fluctuation and the averaged degradation. Within-Device Fluctuation can be directly measured and the averaged degradation can be modelled using the A-G model. The averaged degradation in the A-G model contains: Generated Defects, As-grown Traps and Energy Alternating Defects. These defects have different kinetics against stress time thus need separate modelling. Various patterns such as Stress-Discharge-Recharge, multi-Discharging-based Multiple Pulses are designed to experimentally separate these defects based on their different charging/discharging properties. Fast-Voltage Step Stress technique is developed to reduce the testing time by 90% for the A-G framework parameter extraction, making the framework practical for potential use in industry

DEFECTS AND LIFETIME PREDICTION OF GERMANIUM MOSFETS

To continue improving device speed, much effort has been made to replace Si by high mobility semiconductors. Ge is considered as a strong candidate for pMOSFETs due to the high hole mobility. Two approaches have been demonstrated: high-k/Si-cap/Ge and high-k/GeO2/Ge. Negative Bias Temperature Instability (NBTI) is still one of the main reliability issues, limiting the device lifetime. In this project, it is found that the conventional lifetime prediction method developed for Si is inapplicable to Ge devicesand defect properties in Ge and Si MOSFETs are different.The threshold voltage degradation in Ge can be nearly 100% recovered under a much lower temperature than that in Si devices. The defect losses observed in Si devices were absent in Ge/GeO2/Al2O3. The generation of interface states is insignificant and the positive charges in GeO2/Al2O3 on Ge dominate the NBTI. These positive charges do not follow the same model as those in SiON/Si and an energy-alternating model has been proposed: there are a spread of energy levels of neutral hole traps below Ev andthey lift up after charging, and return below Ev after neutralization.The energy distribution of positive charges in the Al2O3/GeO2/Ge gate stack was studied by the Discharge-based Multi-pulse (DMP) Technique. The different stress-time dependence of defects below Ev and around Ec indicates that they originate from different defects. Quantization effect, Fermi level pinning, and discharge voltage step were considered. The defect differences in terms of the energy level were investigated by using the DMP technique and the energy alternating model is verified by the defect energy distribution.Based on the understanding of different defect behavior, a new NBTI lifetime prediction method was developed for Ge MOSFETs. Energy alternating defects were separated from as-grown hole traps (AHT), which enables to restore the power law for NBTI kinetics with a constant power exponent. The newly developed Ge method was applicable for NBTI lifetime prediction of the state-of-the-art Si-cap/Ge and GeO2/Ge MOSFETs. When compared with SiON/Si, the optimized Si-cap/Ge shows superior reliability, while GeO2/Ge is inferior and needs further optimization. Preliminary characterization was also carried out to investigate the impacts of energy levels and characteristic times of different defects on the frequency and duty factor dependence of AC NBTI degradation

Modeling the Interdependences between Voltage Fluctuation and BTI Aging

With technology scaling, the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to bias temperature instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this paper, we are reporting for the first time that there are interdependences between voltage fluctuation and BTI aging that are nonnegligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, “what is an efficient (i.e., small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?” This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency, and duty cycle conditions. To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IR-drop effects independently, as done in the state of the art, leads to employing insufficient and thus unreliable guardbands because of the nonnegligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependences between aging and IR-drop does not only allow correct guardband estimations, but it also results in employing more efficient guardbands

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book