A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication

The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB) communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s wireless communications. Frequency synthesis in these communication systems involves great challenges such as high frequency and wideband operation in addition to stringent requirements on frequency hopping time and coexistence with other wireless standards. This research proposes frequency generation schemes for such radio systems and their integrated implementations in silicon based technologies. Special emphasis is placed on efficient frequency planning and other system level considerations for building compact and practical systems for carrier frequency generation in an integrated UWB radio. This work proposes a frequency band plan for multiband OFDM based UWB radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency synthesizers are designed, implemented and tested making them one of the first frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband (SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of 2.25 mm2. Finally, an architecture for a UWB synthesizer is proposed that is based on a single multiband quadrature VCO, a programmable integer divider with 50% duty cycle and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the tuning range requirement of the multiband VCO and leads to a very digitally intensive architecture for wideband frequency synthesis suitable for implementation in deep submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while consuming 90 mW. This architecture provides an efficient solution in terms of area and power consumption with very low complexity

High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation

Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication

The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB) communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s wireless communications. Frequency synthesis in these communication systems involves great challenges such as high frequency and wideband operation in addition to stringent requirements on frequency hopping time and coexistence with other wireless standards. This research proposes frequency generation schemes for such radio systems and their integrated implementations in silicon based technologies. Special emphasis is placed on efficient frequency planning and other system level considerations for building compact and practical systems for carrier frequency generation in an integrated UWB radio. This work proposes a frequency band plan for multiband OFDM based UWB radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency synthesizers are designed, implemented and tested making them one of the first frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband (SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of 2.25 mm2. Finally, an architecture for a UWB synthesizer is proposed that is based on a single multiband quadrature VCO, a programmable integer divider with 50% duty cycle and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the tuning range requirement of the multiband VCO and leads to a very digitally intensive architecture for wideband frequency synthesis suitable for implementation in deep submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while consuming 90 mW. This architecture provides an efficient solution in terms of area and power consumption with very low complexity

Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

UWB Low Power RF System for Localization

Real time indoor positioning awareness systems aim to add localization capabilities to upcoming wireless technologies that are quickly becoming an important feature for indoor environment. RF-based impulse-radio ultra-wideband (IR-UWB) is a promising technology for in-door positioning systems due to obstacle penetration capabilities, immunity to multi-path and fading, and high resolution. Major challenge for IR-UWB systems is to achieve higher sensitivity, which puts high sampling demands on receivers, increasing the cost and power consumption. This research concentrates on the design of low power ultra-wideband transceivers and analyses different performance trade-offs. The first part focuses on the trade-off and benefits of UWB for indoor localization. It also discusses battery-less wirelessly-powered UWB transceivers tags, power scavenging for low power wireless sensor networks. In the second part, a low power indoor localization system is proposed and design of low power interference tolerant RF receiver front-end is also presented. Finally, a wide-band inductor-less balun low-noise amplifier (LNA) is demonstrated. To achieve good noise figure, linearity and low power consumption, it exploits a current reuse input common source (CS) stage with source follower (SF) feedback and admittance scaled CS stage for noise and distortion cancellation. By separating gain and input match with active feedback, a higher gain is achieved. This architecture significantly decreases required area and provides high RF gain allowing for higher sensitivity with non-coherent RF receiver architecture

Radio-frequency integrated-circuit design for CMOS single-chip UWB systems

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current

UWB Technology

Ultra Wide Band (UWB) technology has attracted increasing interest and there is a growing demand for UWB for several applications and scenarios. The unlicensed use of the UWB spectrum has been regulated by the Federal Communications Commission (FCC) since the early 2000s. The main concern in designing UWB circuits is to consider the assigned bandwidth and the low power permitted for transmission. This makes UWB circuit design a challenging mission in today's community. Various circuit designs and system implementations are published in this book to give the reader a glimpse of the state-of-the-art examples in this field. The book starts at the circuit level design of major UWB elements such as filters, antennas, and amplifiers; and ends with the complete system implementation using such modules