Towards a Distributed Quantum Computing Ecosystem

The Quantum Internet, by enabling quantum communications among remote quantum nodes, is a network capable of supporting functionalities with no direct counterpart in the classical world. Indeed, with the network and communications functionalities provided by the Quantum Internet, remote quantum devices can communicate and cooperate for solving challenging computational tasks by adopting a distributed computing approach. The aim of this paper is to provide the reader with an overview about the main challenges and open problems arising with the design of a Distributed Quantum Computing ecosystem. For this, we provide a survey, following a bottom-up approach, from a communications engineering perspective. We start by introducing the Quantum Internet as the fundamental underlying infrastructure of the Distributed Quantum Computing ecosystem. Then we go further, by elaborating on a high-level system abstraction of the Distributed Quantum Computing ecosystem. Such an abstraction is described through a set of logical layers. Thereby, we clarify dependencies among the aforementioned layers and, at the same time, a road-map emerges

Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system

Distributed Feature Extraction Using Cloud Computing Resources

The need to expand the computational resources in a massive surveillance network is clear but traditional means of purchasing new equipment for short-term tasks every year is wasteful. In this work I will provide evidence in support of utilizing a cloud computing infrastructure to perform computationally intensive feature extraction tasks on data streams. Efficient off-loading of computational tasks to cloud resources will require a minimization of the time needed to expand the cloud resources, an efficient model of communication and a study of the interplay between the in-network computational resources and remote resources in the cloud. This report provides strong evidence that the use of cloud computing resources in a near real-time distributed sensor network surveillance system, ASAP, is feasible. A face detection web service operating on an Amazon EC2 instance is shown to provide processing of 10-15 frames per second.Umakishore Ramachandran - Faculty Mentor ; Rajnish Kumar - Committee Member/Second Reade

Ianus: an Adpative FPGA Computer

Dedicated machines designed for specific computational algorithms can outperform conventional computers by several orders of magnitude. In this note we describe {\it Ianus}, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability. Our goal is to build a machine that can fully exploit the performance potential of new generation FPGA devices. We also plan a software platform which simplifies its programming, in order to extend its intended range of application to a wide class of interesting and computationally demanding problems. The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their performance increase, as predicted by Moore's law. We discuss this point in detail

Price Discovery and the Accuracy of Consolidated Data Feeds in the U.S. Equity Markets

Both the scientific community and the popular press have paid much attention to the speed of the Securities Information Processor, the data feed consolidating all trades and quotes across the US stock market. Rather than the speed of the Securities Information Processor, or SIP, we focus here on its accuracy. Relying on Trade and Quote data, we provide various measures of SIP latency relative to high-speed data feeds between exchanges, known as direct feeds. We use first differences to highlight not only the divergence between the direct feeds and the SIP, but also the fundamental inaccuracy of the SIP. We find that as many as 60 percent or more of trades are reported out of sequence for stocks with high trade volume, therefore skewing simple measures such as returns. While not yet definitive, this analysis supports our preliminary conclusion that the underlying infrastructure of the SIP is currently unable to keep pace with the trading activity in today's stock market.Comment: 18 pages, 20 figures, 2 table

Constructing cluster of simple FPGA boards for cryptologic computations

In this paper, we propose an FPGA cluster infrastructure, which can be utilized in implementing cryptanalytic attacks and accelerating cryptographic operations. The cluster can be formed using simple and inexpensive, off-the-shelf FPGA boards featuring an FPGA device, local storage, CPLD, and network connection. Forming the cluster is simple and no effort for the hardware development is needed except for the hardware design for the actual computation. Using a softcore processor on FPGA, we are able to configure FPGA devices dynamically and change their configuration on the fly from a remote computer. The softcore on FPGA can execute relatively complicated programs for mundane tasks unworthy of FPGA resources. Finally, we propose and implement a fast and efficient dynamic configuration switch technique that is shown to be useful especially in cryptanalytic applications. Our infrastructure provides a cost-effective alternative for formerly proposed cryptanalytic engines based on FPGA devices